spi.h File Reference

#include "spi_register.h"
#include "ets_sys.h"
#include "osapi.h"
#include "os_type.h"

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Go to the source code of this file.

Macros
#define	SPI   0
#define	HSPI   1
#define	SPI_CLK_USE_DIV   0
#define	SPI_CLK_80MHZ_NODIV   1
#define	SPI_BYTE_ORDER_HIGH_TO_LOW   1
#define	SPI_BYTE_ORDER_LOW_TO_HIGH   0
#define	CPU_CLK_FREQ   80*1000000
#define	SPI_CLK_PREDIV   10
#define	SPI_CLK_CNTDIV   2
#define	SPI_CLK_FREQ   CPU_CLK_FREQ/(SPI_CLK_PREDIV*SPI_CLK_CNTDIV)
#define	spi_busy(spi_no)   READ_PERI_REG(SPI_CMD(spi_no))&SPI_USR
#define	spi_txd(spi_no, bits, data)   spi_transaction(spi_no, 0, 0, 0, 0, bits, (uint32) data, 0, 0)
#define	spi_tx8(spi_no, data)   spi_transaction(spi_no, 0, 0, 0, 0, 8, (uint32) data, 0, 0)
#define	spi_tx16(spi_no, data)   spi_transaction(spi_no, 0, 0, 0, 0, 16, (uint32) data, 0, 0)
#define	spi_tx32(spi_no, data)   spi_transaction(spi_no, 0, 0, 0, 0, 32, (uint32) data, 0, 0)
#define	spi_rxd(spi_no, bits)   spi_transaction(spi_no, 0, 0, 0, 0, 0, 0, bits, 0)
#define	spi_rx8(spi_no)   spi_transaction(spi_no, 0, 0, 0, 0, 0, 0, 8, 0)
#define	spi_rx16(spi_no)   spi_transaction(spi_no, 0, 0, 0, 0, 0, 0, 16, 0)
#define	spi_rx32(spi_no)   spi_transaction(spi_no, 0, 0, 0, 0, 0, 0, 32, 0)

Functions
ICACHE_FLASH_ATTR void	spi_init (uint8 spi_no)
ICACHE_FLASH_ATTR void	spi_mode (uint8 spi_no, uint8 spi_cpha, uint8 spi_cpol)
ICACHE_FLASH_ATTR void	spi_init_gpio (uint8 spi_no, uint8 sysclk_as_spiclk)
ICACHE_FLASH_ATTR void	spi_clock (uint8 spi_no, uint16 prediv, uint8 cntdiv)
ICACHE_FLASH_ATTR void	spi_tx_byte_order (uint8 spi_no, uint8 byte_order)
ICACHE_FLASH_ATTR void	spi_rx_byte_order (uint8 spi_no, uint8 byte_order)
ICACHE_FLASH_ATTR uint32	spi_transaction (uint8 spi_no, uint8 cmd_bits, uint16 cmd_data, uint32 addr_bits, uint32 addr_data, uint32 dout_bits, uint32 dout_data, uint32 din_bits, uint32 dummy_bits)

Macro Definition Documentation

CPU_CLK_FREQ

#define CPU_CLK_FREQ   80*1000000

Definition at line 45 of file spi.h.

HSPI

#define HSPI   1

Definition at line 36 of file spi.h.

Referenced by ext_spi_flash_erase_sector(), ext_spi_flash_id(), ext_spi_flash_read(), ext_spi_flash_write(), ext_spi_init(), and spi_init_gpio().

SPI

#define SPI   0

Definition at line 35 of file spi.h.

Referenced by spi_init_gpio().

spi_busy

#define spi_busy

(

spi_no

)

READ_PERI_REG(SPI_CMD(spi_no))&SPI_USR

Definition at line 66 of file spi.h.

Referenced by spi_transaction().

SPI_BYTE_ORDER_HIGH_TO_LOW

#define SPI_BYTE_ORDER_HIGH_TO_LOW   1

Definition at line 41 of file spi.h.

Referenced by spi_init().

SPI_BYTE_ORDER_LOW_TO_HIGH

#define SPI_BYTE_ORDER_LOW_TO_HIGH   0

Definition at line 42 of file spi.h.

Referenced by ext_spi_init().

SPI_CLK_80MHZ_NODIV

#define SPI_CLK_80MHZ_NODIV   1

Definition at line 39 of file spi.h.

SPI_CLK_CNTDIV

#define SPI_CLK_CNTDIV   2

Definition at line 50 of file spi.h.

Referenced by spi_init().

SPI_CLK_FREQ

#define SPI_CLK_FREQ   CPU_CLK_FREQ/(SPI_CLK_PREDIV*SPI_CLK_CNTDIV)

Definition at line 51 of file spi.h.

SPI_CLK_PREDIV

#define SPI_CLK_PREDIV   10

Definition at line 49 of file spi.h.

Referenced by spi_init().

SPI_CLK_USE_DIV

#define SPI_CLK_USE_DIV   0

Definition at line 38 of file spi.h.

Referenced by ext_spi_init(), and spi_init().

spi_rx16

#define spi_rx16

(

spi_no

)

spi_transaction(spi_no, 0, 0, 0, 0, 0, 0, 16, 0)

Definition at line 75 of file spi.h.

spi_rx32

#define spi_rx32

(

spi_no

)

spi_transaction(spi_no, 0, 0, 0, 0, 0, 0, 32, 0)

Definition at line 76 of file spi.h.

spi_rx8

#define spi_rx8

(

spi_no

)

spi_transaction(spi_no, 0, 0, 0, 0, 0, 0, 8, 0)

Definition at line 74 of file spi.h.

spi_rxd

#define spi_rxd	(		spi_no,
			bits
	)		spi_transaction(spi_no, 0, 0, 0, 0, 0, 0, bits, 0)

Definition at line 73 of file spi.h.

spi_tx16

#define spi_tx16	(		spi_no,
			data
	)		spi_transaction(spi_no, 0, 0, 0, 0, 16, (uint32) data, 0, 0)

Definition at line 70 of file spi.h.

spi_tx32

#define spi_tx32	(		spi_no,
			data
	)		spi_transaction(spi_no, 0, 0, 0, 0, 32, (uint32) data, 0, 0)

Definition at line 71 of file spi.h.

spi_tx8

#define spi_tx8	(		spi_no,
			data
	)		spi_transaction(spi_no, 0, 0, 0, 0, 8, (uint32) data, 0, 0)

Definition at line 69 of file spi.h.

spi_txd

#define spi_txd	(		spi_no,
			bits,
			data
	)		spi_transaction(spi_no, 0, 0, 0, 0, bits, (uint32) data, 0, 0)

Definition at line 68 of file spi.h.

Function Documentation

spi_clock()

ICACHE_FLASH_ATTR void spi_clock	(	uint8	spi_no,
		uint16	prediv,
		uint8	cntdiv
	)

Definition at line 136 of file spi.c.

References ICACHE_FLASH_ATTR, SPI_CLK_EQU_SYSCLK, SPI_CLKCNT_H, SPI_CLKCNT_H_S, SPI_CLKCNT_L, SPI_CLKCNT_L_S, SPI_CLKCNT_N, SPI_CLKCNT_N_S, SPI_CLKDIV_PRE, SPI_CLKDIV_PRE_S, SPI_CLOCK, and WRITE_PERI_REG.

Referenced by ext_spi_init(), and spi_init().

                                                         {
    
    if(spi_no > 1) return;

    if((prediv==0)|(cntdiv==0)){

        WRITE_PERI_REG(SPI_CLOCK(spi_no), SPI_CLK_EQU_SYSCLK);

    } else {
    
        WRITE_PERI_REG(SPI_CLOCK(spi_no), 
                    (((prediv-1)&SPI_CLKDIV_PRE)<<SPI_CLKDIV_PRE_S)|
                    (((cntdiv-1)&SPI_CLKCNT_N)<<SPI_CLKCNT_N_S)|
                    (((cntdiv>>1)&SPI_CLKCNT_H)<<SPI_CLKCNT_H_S)|
                    ((0&SPI_CLKCNT_L)<<SPI_CLKCNT_L_S));
    }

}

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spi_init()

ICACHE_FLASH_ATTR void spi_init

(

uint8

spi_no

)

Definition at line 38 of file spi.c.

References CLEAR_PERI_REG_MASK, ICACHE_FLASH_ATTR, SET_PERI_REG_MASK, SPI_BYTE_ORDER_HIGH_TO_LOW, SPI_CLK_CNTDIV, SPI_CLK_PREDIV, SPI_CLK_USE_DIV, spi_clock(), SPI_CS_HOLD, SPI_CS_SETUP, SPI_FLASH_MODE, spi_init_gpio(), spi_rx_byte_order(), spi_tx_byte_order(), and SPI_USER.

                           {
    
    if(spi_no > 1) return; //Only SPI and HSPI are valid spi modules. 

    spi_init_gpio(spi_no, SPI_CLK_USE_DIV);
    spi_clock(spi_no, SPI_CLK_PREDIV, SPI_CLK_CNTDIV);
    spi_tx_byte_order(spi_no, SPI_BYTE_ORDER_HIGH_TO_LOW);
    spi_rx_byte_order(spi_no, SPI_BYTE_ORDER_HIGH_TO_LOW); 

    SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_CS_SETUP|SPI_CS_HOLD);
    CLEAR_PERI_REG_MASK(SPI_USER(spi_no), SPI_FLASH_MODE);

}

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spi_init_gpio()

ICACHE_FLASH_ATTR void spi_init_gpio	(	uint8	spi_no,
		uint8	sysclk_as_spiclk
	)

Definition at line 97 of file spi.c.

References HSPI, ICACHE_FLASH_ATTR, PERIPHS_IO_MUX, PERIPHS_IO_MUX_MTCK_U, PERIPHS_IO_MUX_MTDI_U, PERIPHS_IO_MUX_MTDO_U, PERIPHS_IO_MUX_MTMS_U, PERIPHS_IO_MUX_SD_CLK_U, PERIPHS_IO_MUX_SD_CMD_U, PERIPHS_IO_MUX_SD_DATA0_U, PERIPHS_IO_MUX_SD_DATA1_U, PIN_FUNC_SELECT, SPI, and WRITE_PERI_REG.

Referenced by ext_spi_init(), and spi_init().

                                                        {

//  if(spi_no > 1) return; //Not required. Valid spi_no is checked with if/elif below.

    uint32 clock_div_flag = 0;
    if(sysclk_as_spiclk){
        clock_div_flag = 0x0001;    
    } 

    if(spi_no==SPI){
        WRITE_PERI_REG(PERIPHS_IO_MUX, 0x005|(clock_div_flag<<8)); //Set bit 8 if 80MHz sysclock required
        PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, 1);
        PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CMD_U, 1);
        PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA0_U, 1);  
        PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA1_U, 1);  
    }else if(spi_no==HSPI){
        WRITE_PERI_REG(PERIPHS_IO_MUX, 0x105|(clock_div_flag<<9)); //Set bit 9 if 80MHz sysclock required
        PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDI_U, 2); //GPIO12 is HSPI MISO pin (Master Data In)
        PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, 2); //GPIO13 is HSPI MOSI pin (Master Data Out)
        PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTMS_U, 2); //GPIO14 is HSPI CLK pin (Clock)
        PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, 2); //GPIO15 is HSPI CS pin (Chip Select / Slave Select)
    }

}

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spi_mode()

ICACHE_FLASH_ATTR void spi_mode	(	uint8	spi_no,
		uint8	spi_cpha,
		uint8	spi_cpol
	)

Definition at line 67 of file spi.c.

References CLEAR_PERI_REG_MASK, ICACHE_FLASH_ATTR, SET_PERI_REG_MASK, SPI_CK_OUT_EDGE, SPI_IDLE_EDGE, SPI_PIN, and SPI_USER.

                                                          {
    if(spi_cpha) {
        CLEAR_PERI_REG_MASK(SPI_USER(spi_no), SPI_CK_OUT_EDGE);
    } else {
        SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_CK_OUT_EDGE);
    }

    if (spi_cpol) {
        SET_PERI_REG_MASK(SPI_PIN(spi_no), SPI_IDLE_EDGE);
    } else {
        CLEAR_PERI_REG_MASK(SPI_PIN(spi_no), SPI_IDLE_EDGE);
    }
}

spi_rx_byte_order()

ICACHE_FLASH_ATTR void spi_rx_byte_order	(	uint8	spi_no,
		uint8	byte_order
	)

Definition at line 207 of file spi.c.

References CLEAR_PERI_REG_MASK, ICACHE_FLASH_ATTR, SET_PERI_REG_MASK, SPI_RD_BYTE_ORDER, and SPI_USER.

Referenced by ext_spi_init(), and spi_init().

                                                      {

    if(spi_no > 1) return;

    if(byte_order){
        SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_RD_BYTE_ORDER);
    } else {
        CLEAR_PERI_REG_MASK(SPI_USER(spi_no), SPI_RD_BYTE_ORDER);
    }
}

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spi_transaction()

ICACHE_FLASH_ATTR uint32 spi_transaction	(	uint8	spi_no,
		uint8	cmd_bits,
		uint16	cmd_data,
		uint32	addr_bits,
		uint32	addr_data,
		uint32	dout_bits,
		uint32	dout_data,
		uint32	din_bits,
		uint32	dummy_bits
	)

Definition at line 241 of file spi.c.

References CLEAR_PERI_REG_MASK, READ_PERI_REG, SET_PERI_REG_MASK, SPI_ADDR, spi_busy, SPI_CMD, SPI_RD_BYTE_ORDER, SPI_USER, SPI_USER1, SPI_USER2, SPI_USR, SPI_USR_ADDR, SPI_USR_ADDR_BITLEN, SPI_USR_ADDR_BITLEN_S, SPI_USR_COMMAND, SPI_USR_COMMAND_BITLEN, SPI_USR_COMMAND_BITLEN_S, SPI_USR_COMMAND_VALUE, SPI_USR_DUMMY, SPI_USR_DUMMY_CYCLELEN, SPI_USR_DUMMY_CYCLELEN_S, SPI_USR_MISO, SPI_USR_MISO_BITLEN, SPI_USR_MISO_BITLEN_S, SPI_USR_MOSI, SPI_USR_MOSI_BITLEN, SPI_USR_MOSI_BITLEN_S, SPI_W0, SPI_WR_BYTE_ORDER, and WRITE_PERI_REG.

Referenced by ext_spi_flash_erase_sector(), ext_spi_flash_id(), ext_spi_flash_read(), and ext_spi_flash_write().

                                                   {

    if(spi_no > 1) return 0;  //Check for a valid SPI 

    //code for custom Chip Select as GPIO PIN here

    while(spi_busy(spi_no)); //wait for SPI to be ready 

//########## Enable SPI Functions ##########//
    //disable MOSI, MISO, ADDR, COMMAND, DUMMY in case previously set.
    CLEAR_PERI_REG_MASK(SPI_USER(spi_no), SPI_USR_MOSI|SPI_USR_MISO|SPI_USR_COMMAND|SPI_USR_ADDR|SPI_USR_DUMMY);

    //enable functions based on number of bits. 0 bits = disabled. 
    //This is rather inefficient but allows for a very generic function.
    //CMD ADDR and MOSI are set below to save on an extra if statement.
//  if(cmd_bits) {SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_USR_COMMAND);}
//  if(addr_bits) {SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_USR_ADDR);}
    if(din_bits) {SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_USR_MISO);}
    if(dummy_bits) {SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_USR_DUMMY);}
//########## END SECTION ##########//

//########## Setup Bitlengths ##########//
    WRITE_PERI_REG(SPI_USER1(spi_no), ((addr_bits-1)&SPI_USR_ADDR_BITLEN)<<SPI_USR_ADDR_BITLEN_S | //Number of bits in Address
                                      ((dout_bits-1)&SPI_USR_MOSI_BITLEN)<<SPI_USR_MOSI_BITLEN_S | //Number of bits to Send
                                      ((din_bits-1)&SPI_USR_MISO_BITLEN)<<SPI_USR_MISO_BITLEN_S |  //Number of bits to receive
                                      ((dummy_bits-1)&SPI_USR_DUMMY_CYCLELEN)<<SPI_USR_DUMMY_CYCLELEN_S); //Number of Dummy bits to insert
//########## END SECTION ##########//

//########## Setup Command Data ##########//
    if(cmd_bits) {
        SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_USR_COMMAND); //enable COMMAND function in SPI module
        uint16 command = cmd_data << (16-cmd_bits); //align command data to high bits
        command = ((command>>8)&0xff) | ((command<<8)&0xff00); //swap byte order
        WRITE_PERI_REG(SPI_USER2(spi_no), ((((cmd_bits-1)&SPI_USR_COMMAND_BITLEN)<<SPI_USR_COMMAND_BITLEN_S) | command&SPI_USR_COMMAND_VALUE)); 
    }
//########## END SECTION ##########//

//########## Setup Address Data ##########//
    if(addr_bits){
        SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_USR_ADDR); //enable ADDRess function in SPI module
        WRITE_PERI_REG(SPI_ADDR(spi_no), addr_data<<(32-addr_bits)); //align address data to high bits
    }
    

//########## END SECTION ##########//   

//########## Setup DOUT data ##########//
    if(dout_bits) {
        SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_USR_MOSI); //enable MOSI function in SPI module
    //copy data to W0
    if(READ_PERI_REG(SPI_USER(spi_no))&SPI_WR_BYTE_ORDER) {
        WRITE_PERI_REG(SPI_W0(spi_no), dout_data<<(32-dout_bits));
    } else {

        uint8 dout_extra_bits = dout_bits%8;

        if(dout_extra_bits){
            //if your data isn't a byte multiple (8/16/24/32 bits)and you don't have SPI_WR_BYTE_ORDER set, you need this to move the non-8bit remainder to the MSBs
            //not sure if there's even a use case for this, but it's here if you need it...
            //for example, 0xDA4 12 bits without SPI_WR_BYTE_ORDER would usually be output as if it were 0x0DA4, 
            //of which 0xA4, and then 0x0 would be shifted out (first 8 bits of low byte, then 4 MSB bits of high byte - ie reverse byte order). 
            //The code below shifts it out as 0xA4 followed by 0xD as you might require. 
            WRITE_PERI_REG(SPI_W0(spi_no), ((0xFFFFFFFF<<(dout_bits - dout_extra_bits)&dout_data)<<(8-dout_extra_bits) | (0xFFFFFFFF>>(32-(dout_bits - dout_extra_bits)))&dout_data));
        } else {
            WRITE_PERI_REG(SPI_W0(spi_no), dout_data);
        }
    }
    }
//########## END SECTION ##########//

//########## Begin SPI Transaction ##########//
    SET_PERI_REG_MASK(SPI_CMD(spi_no), SPI_USR);
//########## END SECTION ##########//

//########## Return DIN data ##########//
    if(din_bits) {
        while(spi_busy(spi_no));    //wait for SPI transaction to complete
        
        if(READ_PERI_REG(SPI_USER(spi_no))&SPI_RD_BYTE_ORDER) {
            return READ_PERI_REG(SPI_W0(spi_no)) >> (32-din_bits); //Assuming data in is written to MSB. TBC
        } else {
            return READ_PERI_REG(SPI_W0(spi_no)); //Read in the same way as DOUT is sent. Note existing contents of SPI_W0 remain unless overwritten! 
        }

        return 0; //something went wrong
    }
//########## END SECTION ##########//

    //Transaction completed
    return 1; //success
}

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spi_tx_byte_order()

ICACHE_FLASH_ATTR void spi_tx_byte_order	(	uint8	spi_no,
		uint8	byte_order
	)

Definition at line 176 of file spi.c.

References CLEAR_PERI_REG_MASK, ICACHE_FLASH_ATTR, SET_PERI_REG_MASK, SPI_USER, and SPI_WR_BYTE_ORDER.

Referenced by ext_spi_init(), and spi_init().

                                                      {

    if(spi_no > 1) return;

    if(byte_order){
        SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_WR_BYTE_ORDER);
    } else {
        CLEAR_PERI_REG_MASK(SPI_USER(spi_no), SPI_WR_BYTE_ORDER);
    }
}

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