MeterLogger
spi_register.h
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1 /*
2  * Copyright (c) 2010 - 2011 Espressif System
3  * Modified by David Ogilvy (MetalPhreak)
4  * Based on original file included in SDK 1.0.0
5  *
6  * Missing defines from previous SDK versions have
7  * been added and are noted with comments. The
8  * names of these defines are likely to change.
9  */
10 
11 #ifndef SPI_REGISTER_H_INCLUDED
12 #define SPI_REGISTER_H_INCLUDED
13 
14 #define REG_SPI_BASE(i) (0x60000200-i*0x100)
15 
16 #define SPI_CMD(i) (REG_SPI_BASE(i) + 0x0)
17 #define SPI_FLASH_READ (BIT(31)) //From previous SDK
18 #define SPI_FLASH_WREN (BIT(30)) //From previous SDK
19 #define SPI_FLASH_WRDI (BIT(29)) //From previous SDK
20 #define SPI_FLASH_RDID (BIT(28)) //From previous SDK
21 #define SPI_FLASH_RDSR (BIT(27)) //From previous SDK
22 #define SPI_FLASH_WRSR (BIT(26)) //From previous SDK
23 #define SPI_FLASH_PP (BIT(25)) //From previous SDK
24 #define SPI_FLASH_SE (BIT(24)) //From previous SDK
25 #define SPI_FLASH_BE (BIT(23)) //From previous SDK
26 #define SPI_FLASH_CE (BIT(22)) //From previous SDK
27 #define SPI_FLASH_DP (BIT(21)) //From previous SDK
28 #define SPI_FLASH_RES (BIT(20)) //From previous SDK
29 #define SPI_FLASH_HPM (BIT(19)) //From previous SDK
30 #define SPI_USR (BIT(18))
31 
32 #define SPI_ADDR(i) (REG_SPI_BASE(i) + 0x4)
33 
34 #define SPI_CTRL(i) (REG_SPI_BASE(i) + 0x8)
35 #define SPI_WR_BIT_ORDER (BIT(26))
36 #define SPI_RD_BIT_ORDER (BIT(25))
37 #define SPI_QIO_MODE (BIT(24))
38 #define SPI_DIO_MODE (BIT(23))
39 #define SPI_TWO_BYTE_STATUS_EN (BIT(22)) //From previous SDK
40 #define SPI_WP_REG (BIT(21)) //From previous SDK
41 #define SPI_QOUT_MODE (BIT(20))
42 #define SPI_SHARE_BUS (BIT(19)) //From previous SDK
43 #define SPI_HOLD_MODE (BIT(18)) //From previous SDK
44 #define SPI_ENABLE_AHB (BIT(17)) //From previous SDK
45 #define SPI_SST_AAI (BIT(16)) //From previous SDK
46 #define SPI_RESANDRES (BIT(15)) //From previous SDK
47 #define SPI_DOUT_MODE (BIT(14))
48 #define SPI_FASTRD_MODE (BIT(13))
49 
50 #define SPI_CTRL1(i) (REG_SPI_BASE (i) + 0xC) //From previous SDK. Removed _FLASH_ from name to match other registers.
51 #define SPI_CS_HOLD_DELAY 0x0000000F //Espressif BBS
52 #define SPI_CS_HOLD_DELAY_S 28 //Espressif BBS
53 #define SPI_CS_HOLD_DELAY_RES 0x00000FFF //Espressif BBS
54 #define SPI_CS_HOLD_DELAY_RES_S 16 //Espressif BBS
55 #define SPI_BUS_TIMER_LIMIT 0x0000FFFF //From previous SDK
56 #define SPI_BUS_TIMER_LIMIT_S 0 //From previous SDK
57 
58 
59 #define SPI_RD_STATUS(i) (REG_SPI_BASE(i) + 0x10)
60 #define SPI_STATUS_EXT 0x000000FF //From previous SDK
61 #define SPI_STATUS_EXT_S 24 //From previous SDK
62 #define SPI_WB_MODE 0x000000FF //From previous SDK
63 #define SPI_WB_MODE_S 16 //From previous SDK
64 #define SPI_FLASH_STATUS_PRO_FLAG (BIT(7)) //From previous SDK
65 #define SPI_FLASH_TOP_BOT_PRO_FLAG (BIT(5)) //From previous SDK
66 #define SPI_FLASH_BP2 (BIT(4)) //From previous SDK
67 #define SPI_FLASH_BP1 (BIT(3)) //From previous SDK
68 #define SPI_FLASH_BP0 (BIT(2)) //From previous SDK
69 #define SPI_FLASH_WRENABLE_FLAG (BIT(1)) //From previous SDK
70 #define SPI_FLASH_BUSY_FLAG (BIT(0)) //From previous SDK
71 
72 #define SPI_CTRL2(i) (REG_SPI_BASE(i) + 0x14)
73 #define SPI_CS_DELAY_NUM 0x0000000F
74 #define SPI_CS_DELAY_NUM_S 28
75 #define SPI_CS_DELAY_MODE 0x00000003
76 #define SPI_CS_DELAY_MODE_S 26
77 #define SPI_MOSI_DELAY_NUM 0x00000007
78 #define SPI_MOSI_DELAY_NUM_S 23
79 #define SPI_MOSI_DELAY_MODE 0x00000003 //mode 0 : posedge; data set at positive edge of clk
80  //mode 1 : negedge + 1 cycle delay, only if freq<10MHz ; data set at negitive edge of clk
81  //mode 2 : Do not use this mode.
82 #define SPI_MOSI_DELAY_MODE_S 21
83 #define SPI_MISO_DELAY_NUM 0x00000007
84 #define SPI_MISO_DELAY_NUM_S 18
85 #define SPI_MISO_DELAY_MODE 0x00000003
86 #define SPI_MISO_DELAY_MODE_S 16
87 #define SPI_CK_OUT_HIGH_MODE 0x0000000F
88 #define SPI_CK_OUT_HIGH_MODE_S 12
89 #define SPI_CK_OUT_LOW_MODE 0x0000000F
90 #define SPI_CK_OUT_LOW_MODE_S 8
91 #define SPI_HOLD_TIME 0x0000000F
92 #define SPI_HOLD_TIME_S 4
93 #define SPI_SETUP_TIME 0x0000000F
94 #define SPI_SETUP_TIME_S 0
95 
96 #define SPI_CLOCK(i) (REG_SPI_BASE(i) + 0x18)
97 #define SPI_CLK_EQU_SYSCLK (BIT(31))
98 #define SPI_CLKDIV_PRE 0x00001FFF
99 #define SPI_CLKDIV_PRE_S 18
100 #define SPI_CLKCNT_N 0x0000003F
101 #define SPI_CLKCNT_N_S 12
102 #define SPI_CLKCNT_H 0x0000003F
103 #define SPI_CLKCNT_H_S 6
104 #define SPI_CLKCNT_L 0x0000003F
105 #define SPI_CLKCNT_L_S 0
106 
107 #define SPI_USER(i) (REG_SPI_BASE(i) + 0x1C)
108 #define SPI_USR_COMMAND (BIT(31))
109 #define SPI_USR_ADDR (BIT(30))
110 #define SPI_USR_DUMMY (BIT(29))
111 #define SPI_USR_MISO (BIT(28))
112 #define SPI_USR_MOSI (BIT(27))
113 #define SPI_USR_DUMMY_IDLE (BIT(26)) //From previous SDK
114 #define SPI_USR_MOSI_HIGHPART (BIT(25))
115 #define SPI_USR_MISO_HIGHPART (BIT(24))
116 #define SPI_USR_PREP_HOLD (BIT(23)) //From previous SDK
117 #define SPI_USR_CMD_HOLD (BIT(22)) //From previous SDK
118 #define SPI_USR_ADDR_HOLD (BIT(21)) //From previous SDK
119 #define SPI_USR_DUMMY_HOLD (BIT(20)) //From previous SDK
120 #define SPI_USR_DIN_HOLD (BIT(19)) //From previous SDK
121 #define SPI_USR_DOUT_HOLD (BIT(18)) //From previous SDK
122 #define SPI_USR_HOLD_POL (BIT(17)) //From previous SDK
123 #define SPI_SIO (BIT(16))
124 #define SPI_FWRITE_QIO (BIT(15))
125 #define SPI_FWRITE_DIO (BIT(14))
126 #define SPI_FWRITE_QUAD (BIT(13))
127 #define SPI_FWRITE_DUAL (BIT(12))
128 #define SPI_WR_BYTE_ORDER (BIT(11))
129 #define SPI_RD_BYTE_ORDER (BIT(10))
130 #define SPI_AHB_ENDIAN_MODE 0x00000003 //From previous SDK
131 #define SPI_AHB_ENDIAN_MODE_S 8 //From previous SDK
132 #define SPI_CK_OUT_EDGE (BIT(7))
133 #define SPI_CK_I_EDGE (BIT(6))
134 #define SPI_CS_SETUP (BIT(5))
135 #define SPI_CS_HOLD (BIT(4))
136 #define SPI_AHB_USR_COMMAND (BIT(3)) //From previous SDK
137 #define SPI_FLASH_MODE (BIT(2))
138 #define SPI_AHB_USR_COMMAND_4BYTE (BIT(1)) //From previous SDK
139 #define SPI_DOUTDIN (BIT(0)) //From previous SDK
140 
141 //AHB = http://en.wikipedia.org/wiki/Advanced_Microcontroller_Bus_Architecture ?
142 
143 
144 #define SPI_USER1(i) (REG_SPI_BASE(i) + 0x20)
145 #define SPI_USR_ADDR_BITLEN 0x0000003F
146 #define SPI_USR_ADDR_BITLEN_S 26
147 #define SPI_USR_MOSI_BITLEN 0x000001FF
148 #define SPI_USR_MOSI_BITLEN_S 17
149 #define SPI_USR_MISO_BITLEN 0x000001FF
150 #define SPI_USR_MISO_BITLEN_S 8
151 #define SPI_USR_DUMMY_CYCLELEN 0x000000FF
152 #define SPI_USR_DUMMY_CYCLELEN_S 0
153 
154 #define SPI_USER2(i) (REG_SPI_BASE(i) + 0x24)
155 #define SPI_USR_COMMAND_BITLEN 0x0000000F
156 #define SPI_USR_COMMAND_BITLEN_S 28
157 #define SPI_USR_COMMAND_VALUE 0x0000FFFF
158 #define SPI_USR_COMMAND_VALUE_S 0
159 
160 #define SPI_WR_STATUS(i) (REG_SPI_BASE(i) + 0x28)
161  //previously defined as SPI_FLASH_USER3. No further info available.
162 
163 #define SPI_PIN(i) (REG_SPI_BASE(i) + 0x2C)
164 #define SPI_IDLE_EDGE (BIT(29))
165 #define SPI_CS2_DIS (BIT(2))
166 #define SPI_CS1_DIS (BIT(1))
167 #define SPI_CS0_DIS (BIT(0))
168 
169 #define SPI_SLAVE(i) (REG_SPI_BASE(i) + 0x30)
170 #define SPI_SYNC_RESET (BIT(31))
171 #define SPI_SLAVE_MODE (BIT(30))
172 #define SPI_SLV_WR_RD_BUF_EN (BIT(29))
173 #define SPI_SLV_WR_RD_STA_EN (BIT(28))
174 #define SPI_SLV_CMD_DEFINE (BIT(27))
175 #define SPI_TRANS_CNT 0x0000000F
176 #define SPI_TRANS_CNT_S 23
177 #define SPI_SLV_LAST_STATE 0x00000007 //From previous SDK
178 #define SPI_SLV_LAST_STATE_S 20 //From previous SDK
179 #define SPI_SLV_LAST_COMMAND 0x00000007 //From previous SDK
180 #define SPI_SLV_LAST_COMMAND_S 17 //From previous SDK
181 #define SPI_CS_I_MODE 0x00000003 //From previous SDK
182 #define SPI_CS_I_MODE_S 10 //From previous SDK
183 #define SPI_TRANS_DONE_EN (BIT(9))
184 #define SPI_SLV_WR_STA_DONE_EN (BIT(8))
185 #define SPI_SLV_RD_STA_DONE_EN (BIT(7))
186 #define SPI_SLV_WR_BUF_DONE_EN (BIT(6))
187 #define SPI_SLV_RD_BUF_DONE_EN (BIT(5))
188 #define SLV_SPI_INT_EN 0x0000001f
189 #define SLV_SPI_INT_EN_S 5
190 #define SPI_TRANS_DONE (BIT(4))
191 #define SPI_SLV_WR_STA_DONE (BIT(3))
192 #define SPI_SLV_RD_STA_DONE (BIT(2))
193 #define SPI_SLV_WR_BUF_DONE (BIT(1))
194 #define SPI_SLV_RD_BUF_DONE (BIT(0))
195 
196 #define SPI_SLAVE1(i) (REG_SPI_BASE(i) + 0x34)
197 #define SPI_SLV_STATUS_BITLEN 0x0000001F
198 #define SPI_SLV_STATUS_BITLEN_S 27
199 #define SPI_SLV_STATUS_FAST_EN (BIT(26)) //From previous SDK
200 #define SPI_SLV_STATUS_READBACK (BIT(25)) //From previous SDK
201 #define SPI_SLV_BUF_BITLEN 0x000001FF
202 #define SPI_SLV_BUF_BITLEN_S 16
203 #define SPI_SLV_RD_ADDR_BITLEN 0x0000003F
204 #define SPI_SLV_RD_ADDR_BITLEN_S 10
205 #define SPI_SLV_WR_ADDR_BITLEN 0x0000003F
206 #define SPI_SLV_WR_ADDR_BITLEN_S 4
207 #define SPI_SLV_WRSTA_DUMMY_EN (BIT(3))
208 #define SPI_SLV_RDSTA_DUMMY_EN (BIT(2))
209 #define SPI_SLV_WRBUF_DUMMY_EN (BIT(1))
210 #define SPI_SLV_RDBUF_DUMMY_EN (BIT(0))
211 
212 
213 
214 #define SPI_SLAVE2(i) (REG_SPI_BASE(i) + 0x38)
215 #define SPI_SLV_WRBUF_DUMMY_CYCLELEN 0X000000FF
216 #define SPI_SLV_WRBUF_DUMMY_CYCLELEN_S 24
217 #define SPI_SLV_RDBUF_DUMMY_CYCLELEN 0X000000FF
218 #define SPI_SLV_RDBUF_DUMMY_CYCLELEN_S 16
219 #define SPI_SLV_WRSTR_DUMMY_CYCLELEN 0X000000FF
220 #define SPI_SLV_WRSTR_DUMMY_CYCLELEN_S 8
221 #define SPI_SLV_RDSTR_DUMMY_CYCLELEN 0x000000FF
222 #define SPI_SLV_RDSTR_DUMMY_CYCLELEN_S 0
223 
224 #define SPI_SLAVE3(i) (REG_SPI_BASE(i) + 0x3C)
225 #define SPI_SLV_WRSTA_CMD_VALUE 0x000000FF
226 #define SPI_SLV_WRSTA_CMD_VALUE_S 24
227 #define SPI_SLV_RDSTA_CMD_VALUE 0x000000FF
228 #define SPI_SLV_RDSTA_CMD_VALUE_S 16
229 #define SPI_SLV_WRBUF_CMD_VALUE 0x000000FF
230 #define SPI_SLV_WRBUF_CMD_VALUE_S 8
231 #define SPI_SLV_RDBUF_CMD_VALUE 0x000000FF
232 #define SPI_SLV_RDBUF_CMD_VALUE_S 0
233 
234 //Previous SDKs referred to these following registers as SPI_C0 etc.
235 
236 #define SPI_W0(i) (REG_SPI_BASE(i) +0x40)
237 #define SPI_W1(i) (REG_SPI_BASE(i) +0x44)
238 #define SPI_W2(i) (REG_SPI_BASE(i) +0x48)
239 #define SPI_W3(i) (REG_SPI_BASE(i) +0x4C)
240 #define SPI_W4(i) (REG_SPI_BASE(i) +0x50)
241 #define SPI_W5(i) (REG_SPI_BASE(i) +0x54)
242 #define SPI_W6(i) (REG_SPI_BASE(i) +0x58)
243 #define SPI_W7(i) (REG_SPI_BASE(i) +0x5C)
244 #define SPI_W8(i) (REG_SPI_BASE(i) +0x60)
245 #define SPI_W9(i) (REG_SPI_BASE(i) +0x64)
246 #define SPI_W10(i) (REG_SPI_BASE(i) +0x68)
247 #define SPI_W11(i) (REG_SPI_BASE(i) +0x6C)
248 #define SPI_W12(i) (REG_SPI_BASE(i) +0x70)
249 #define SPI_W13(i) (REG_SPI_BASE(i) +0x74)
250 #define SPI_W14(i) (REG_SPI_BASE(i) +0x78)
251 #define SPI_W15(i) (REG_SPI_BASE(i) +0x7C)
252 
253  // +0x80 to +0xBC could be SPI_W16 through SPI_W31?
254 
255  // +0xC0 to +0xEC not currently defined.
256 
257 #define SPI_EXT0(i) (REG_SPI_BASE(i) + 0xF0) //From previous SDK. Removed _FLASH_ from name to match other registers.
258 #define SPI_T_PP_ENA (BIT(31)) //From previous SDK
259 #define SPI_T_PP_SHIFT 0x0000000F //From previous SDK
260 #define SPI_T_PP_SHIFT_S 16 //From previous SDK
261 #define SPI_T_PP_TIME 0x00000FFF //From previous SDK
262 #define SPI_T_PP_TIME_S 0 //From previous SDK
263 
264 #define SPI_EXT1(i) (REG_SPI_BASE(i) + 0xF4) //From previous SDK. Removed _FLASH_ from name to match other registers.
265 #define SPI_T_ERASE_ENA (BIT(31)) //From previous SDK
266 #define SPI_T_ERASE_SHIFT 0x0000000F //From previous SDK
267 #define SPI_T_ERASE_SHIFT_S 16 //From previous SDK
268 #define SPI_T_ERASE_TIME 0x00000FFF //From previous SDK
269 #define SPI_T_ERASE_TIME_S 0 //From previous SDK
270 
271 #define SPI_EXT2(i) (REG_SPI_BASE(i) + 0xF8) //From previous SDK. Removed _FLASH_ from name to match other registers.
272 #define SPI_ST 0x00000007 //From previous SDK
273 #define SPI_ST_S 0 //From previous SDK
274 
275 #define SPI_EXT3(i) (REG_SPI_BASE(i) + 0xFC)
276 #define SPI_INT_HOLD_ENA 0x00000003
277 #define SPI_INT_HOLD_ENA_S 0
278 #endif // SPI_REGISTER_H_INCLUDED
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