Go to the documentation of this file. 29 #define BIT31 0x80000000 30 #define BIT30 0x40000000 31 #define BIT29 0x20000000 32 #define BIT28 0x10000000 33 #define BIT27 0x08000000 34 #define BIT26 0x04000000 35 #define BIT25 0x02000000 36 #define BIT24 0x01000000 37 #define BIT23 0x00800000 38 #define BIT22 0x00400000 39 #define BIT21 0x00200000 40 #define BIT20 0x00100000 41 #define BIT19 0x00080000 42 #define BIT18 0x00040000 43 #define BIT17 0x00020000 44 #define BIT16 0x00010000 45 #define BIT15 0x00008000 46 #define BIT14 0x00004000 47 #define BIT13 0x00002000 48 #define BIT12 0x00001000 49 #define BIT11 0x00000800 50 #define BIT10 0x00000400 51 #define BIT9 0x00000200 52 #define BIT8 0x00000100 53 #define BIT7 0x00000080 54 #define BIT6 0x00000040 55 #define BIT5 0x00000020 56 #define BIT4 0x00000010 57 #define BIT3 0x00000008 58 #define BIT2 0x00000004 59 #define BIT1 0x00000002 60 #define BIT0 0x00000001 64 #define ETS_UNCACHED_ADDR(addr) (addr) 65 #define ETS_CACHED_ADDR(addr) (addr) 68 #define READ_PERI_REG(addr) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) 69 #define WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val) 70 #define CLEAR_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))) 71 #define SET_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))) 72 #define GET_PERI_REG_BITS(reg, hipos,lowpos) ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)) 73 #define SET_PERI_REG_BITS(reg,bit_map,value,shift) (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|((value)<<(shift)) )) 77 #define APB_CLK_FREQ 80*1000000 //unit: Hz 78 #define UART_CLK_FREQ APB_CLK_FREQ 79 #define TIMER_CLK_FREQ (APB_CLK_FREQ>>8) //divided by 256 83 #define PERIPHS_DPORT_BASEADDR 0x3ff00000 84 #define PERIPHS_GPIO_BASEADDR 0x60000300 85 #define PERIPHS_TIMER_BASEDDR 0x60000600 86 #define PERIPHS_RTC_BASEADDR 0x60000700 87 #define PERIPHS_IO_MUX 0x60000800 91 #define EDGE_INT_ENABLE_REG (PERIPHS_DPORT_BASEADDR+0x04) 92 #define TM1_EDGE_INT_ENABLE() SET_PERI_REG_MASK(EDGE_INT_ENABLE_REG, BIT1) 93 #define TM1_EDGE_INT_DISABLE() CLEAR_PERI_REG_MASK(EDGE_INT_ENABLE_REG, BIT1) 97 #define GPIO_REG_READ(reg) READ_PERI_REG(PERIPHS_GPIO_BASEADDR + reg) 98 #define GPIO_REG_WRITE(reg, val) WRITE_PERI_REG(PERIPHS_GPIO_BASEADDR + reg, val) 99 #define GPIO_OUT_ADDRESS 0x00 100 #define GPIO_OUT_W1TS_ADDRESS 0x04 101 #define GPIO_OUT_W1TC_ADDRESS 0x08 103 #define GPIO_ENABLE_ADDRESS 0x0c 104 #define GPIO_ENABLE_W1TS_ADDRESS 0x10 105 #define GPIO_ENABLE_W1TC_ADDRESS 0x14 106 #define GPIO_OUT_W1TC_DATA_MASK 0x0000ffff 108 #define GPIO_IN_ADDRESS 0x18 110 #define GPIO_STATUS_ADDRESS 0x1c 111 #define GPIO_STATUS_W1TS_ADDRESS 0x20 112 #define GPIO_STATUS_W1TC_ADDRESS 0x24 113 #define GPIO_STATUS_INTERRUPT_MASK 0x0000ffff 115 #define GPIO_RTC_CALIB_SYNC PERIPHS_GPIO_BASEADDR+0x6c 116 #define RTC_CALIB_START BIT31 //first write to zero, then to one to start 117 #define RTC_PERIOD_NUM_MASK 0x3ff //max 8ms 118 #define GPIO_RTC_CALIB_VALUE PERIPHS_GPIO_BASEADDR+0x70 119 #define RTC_CALIB_RDY_S 31 //after measure, flag to one, when start from zero to one, turn to zero 120 #define RTC_CALIB_VALUE_MASK 0xfffff 122 #define GPIO_PIN0_ADDRESS 0x28 124 #define GPIO_ID_PIN0 0 125 #define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n)) 126 #define GPIO_LAST_REGISTER_ID GPIO_ID_PIN(15) 127 #define GPIO_ID_NONE 0xffffffff 129 #define GPIO_PIN_COUNT 16 131 #define GPIO_PIN_CONFIG_MSB 12 132 #define GPIO_PIN_CONFIG_LSB 11 133 #define GPIO_PIN_CONFIG_MASK 0x00001800 134 #define GPIO_PIN_CONFIG_GET(x) (((x) & GPIO_PIN_CONFIG_MASK) >> GPIO_PIN_CONFIG_LSB) 135 #define GPIO_PIN_CONFIG_SET(x) (((x) << GPIO_PIN_CONFIG_LSB) & GPIO_PIN_CONFIG_MASK) 137 #define GPIO_WAKEUP_ENABLE 1 138 #define GPIO_WAKEUP_DISABLE (~GPIO_WAKEUP_ENABLE) 139 #define GPIO_PIN_WAKEUP_ENABLE_MSB 10 140 #define GPIO_PIN_WAKEUP_ENABLE_LSB 10 141 #define GPIO_PIN_WAKEUP_ENABLE_MASK 0x00000400 142 #define GPIO_PIN_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN_WAKEUP_ENABLE_MASK) >> GPIO_PIN_WAKEUP_ENABLE_LSB) 143 #define GPIO_PIN_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN_WAKEUP_ENABLE_LSB) & GPIO_PIN_WAKEUP_ENABLE_MASK) 145 #define GPIO_PIN_INT_TYPE_MASK 0x380 146 #define GPIO_PIN_INT_TYPE_MSB 9 147 #define GPIO_PIN_INT_TYPE_LSB 7 148 #define GPIO_PIN_INT_TYPE_GET(x) (((x) & GPIO_PIN_INT_TYPE_MASK) >> GPIO_PIN_INT_TYPE_LSB) 149 #define GPIO_PIN_INT_TYPE_SET(x) (((x) << GPIO_PIN_INT_TYPE_LSB) & GPIO_PIN_INT_TYPE_MASK) 151 #define GPIO_PAD_DRIVER_ENABLE 1 152 #define GPIO_PAD_DRIVER_DISABLE (~GPIO_PAD_DRIVER_ENABLE) 153 #define GPIO_PIN_PAD_DRIVER_MSB 2 154 #define GPIO_PIN_PAD_DRIVER_LSB 2 155 #define GPIO_PIN_PAD_DRIVER_MASK 0x00000004 156 #define GPIO_PIN_PAD_DRIVER_GET(x) (((x) & GPIO_PIN_PAD_DRIVER_MASK) >> GPIO_PIN_PAD_DRIVER_LSB) 157 #define GPIO_PIN_PAD_DRIVER_SET(x) (((x) << GPIO_PIN_PAD_DRIVER_LSB) & GPIO_PIN_PAD_DRIVER_MASK) 159 #define GPIO_AS_PIN_SOURCE 0 160 #define SIGMA_AS_PIN_SOURCE (~GPIO_AS_PIN_SOURCE) 161 #define GPIO_PIN_SOURCE_MSB 0 162 #define GPIO_PIN_SOURCE_LSB 0 163 #define GPIO_PIN_SOURCE_MASK 0x00000001 164 #define GPIO_PIN_SOURCE_GET(x) (((x) & GPIO_PIN_SOURCE_MASK) >> GPIO_PIN_SOURCE_LSB) 165 #define GPIO_PIN_SOURCE_SET(x) (((x) << GPIO_PIN_SOURCE_LSB) & GPIO_PIN_SOURCE_MASK) 169 #define RTC_REG_READ(addr) READ_PERI_REG(PERIPHS_TIMER_BASEDDR + addr) 170 #define RTC_REG_WRITE(addr, val) WRITE_PERI_REG(PERIPHS_TIMER_BASEDDR + addr, val) 171 #define RTC_CLR_REG_MASK(reg, mask) CLEAR_PERI_REG_MASK(PERIPHS_TIMER_BASEDDR +reg, mask) 173 #define NOW() RTC_REG_READ(FRC2_COUNT_ADDRESS) 176 #define FRC1_LOAD_ADDRESS 0x00 179 #define FRC1_COUNT_ADDRESS 0x04 181 #define FRC1_CTRL_ADDRESS 0x08 184 #define FRC1_INT_ADDRESS 0x0c 185 #define FRC1_INT_CLR_MASK 0x00000001 188 #define FRC2_COUNT_ADDRESS 0x24 192 #define REG_RTC_BASE PERIPHS_RTC_BASEADDR 194 #define RTC_STORE0 (REG_RTC_BASE + 0x030) 195 #define RTC_STORE1 (REG_RTC_BASE + 0x034) 196 #define RTC_STORE2 (REG_RTC_BASE + 0x038) 197 #define RTC_STORE3 (REG_RTC_BASE + 0x03C) 199 #define RTC_GPIO_OUT (REG_RTC_BASE + 0x068) 200 #define RTC_GPIO_ENABLE (REG_RTC_BASE + 0x074) 201 #define RTC_GPIO_IN_DATA (REG_RTC_BASE + 0x08C) 202 #define RTC_GPIO_CONF (REG_RTC_BASE + 0x090) 203 #define PAD_XPD_DCDC_CONF (REG_RTC_BASE + 0x0A0) 207 #define PERIPHS_IO_MUX_FUNC 0x13 208 #define PERIPHS_IO_MUX_FUNC_S 4 209 #define PERIPHS_IO_MUX_PULLUP BIT7 210 #define PERIPHS_IO_MUX_PULLUP2 BIT6 211 #define PERIPHS_IO_MUX_SLEEP_PULLUP BIT3 212 #define PERIPHS_IO_MUX_SLEEP_PULLUP2 BIT2 213 #define PERIPHS_IO_MUX_SLEEP_OE BIT1 214 #define PERIPHS_IO_MUX_OE BIT0 216 #define PERIPHS_IO_MUX_CONF_U (PERIPHS_IO_MUX + 0x00) 217 #define SPI0_CLK_EQU_SYS_CLK BIT8 218 #define SPI1_CLK_EQU_SYS_CLK BIT9 219 #define PERIPHS_IO_MUX_MTDI_U (PERIPHS_IO_MUX + 0x04) 220 #define FUNC_GPIO12 3 221 #define PERIPHS_IO_MUX_MTCK_U (PERIPHS_IO_MUX + 0x08) 222 #define FUNC_GPIO13 3 223 #define PERIPHS_IO_MUX_MTMS_U (PERIPHS_IO_MUX + 0x0C) 224 #define FUNC_GPIO14 3 225 #define PERIPHS_IO_MUX_MTDO_U (PERIPHS_IO_MUX + 0x10) 226 #define FUNC_GPIO15 3 228 #define PERIPHS_IO_MUX_U0RXD_U (PERIPHS_IO_MUX + 0x14) 230 #define PERIPHS_IO_MUX_U0TXD_U (PERIPHS_IO_MUX + 0x18) 233 #define PERIPHS_IO_MUX_SD_CLK_U (PERIPHS_IO_MUX + 0x1c) 235 #define FUNC_SPICLK 1 236 #define PERIPHS_IO_MUX_SD_DATA0_U (PERIPHS_IO_MUX + 0x20) 237 #define FUNC_SDDATA0 0 240 #define PERIPHS_IO_MUX_SD_DATA1_U (PERIPHS_IO_MUX + 0x24) 241 #define FUNC_SDDATA1 0 244 #define FUNC_SDDATA1_U1RXD 7 245 #define PERIPHS_IO_MUX_SD_DATA2_U (PERIPHS_IO_MUX + 0x28) 246 #define FUNC_SDDATA2 0 249 #define PERIPHS_IO_MUX_SD_DATA3_U (PERIPHS_IO_MUX + 0x2c) 250 #define FUNC_SDDATA3 0 252 #define FUNC_GPIO10 3 253 #define PERIPHS_IO_MUX_SD_CMD_U (PERIPHS_IO_MUX + 0x30) 255 #define FUNC_SPICS0 1 256 #define PERIPHS_IO_MUX_GPIO0_U (PERIPHS_IO_MUX + 0x34) 258 #define PERIPHS_IO_MUX_GPIO2_U (PERIPHS_IO_MUX + 0x38) 260 #define FUNC_U1TXD_BK 2 261 #define FUNC_U0TXD_BK 4 262 #define PERIPHS_IO_MUX_GPIO4_U (PERIPHS_IO_MUX + 0x3C) 264 #define PERIPHS_IO_MUX_GPIO5_U (PERIPHS_IO_MUX + 0x40) 267 #define PIN_PULLUP_DIS(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME, PERIPHS_IO_MUX_PULLUP) 268 #define PIN_PULLUP_EN(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME, PERIPHS_IO_MUX_PULLUP) 270 #define PIN_FUNC_SELECT(PIN_NAME, FUNC) do { \ 271 WRITE_PERI_REG(PIN_NAME, \ 272 READ_PERI_REG(PIN_NAME) \ 273 & (~(PERIPHS_IO_MUX_FUNC<<PERIPHS_IO_MUX_FUNC_S)) \ 274 |( (((FUNC&BIT2)<<2)|(FUNC&0x3))<<PERIPHS_IO_MUX_FUNC_S) ); \ 279 #endif //_EAGLE_SOC_H_