dphy
Vitis Drivers API Documentation
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Data Structures | |
struct | XDphy_Config |
The configuration structure for DPHY. More... | |
struct | XDphy |
The XDphy Controller driver instance data. More... | |
Macros | |
#define | XDPHY_H_ |
Prevent circular inclusions by using protection macros. More... | |
Functions | |
u32 | XDphy_CfgInitialize (XDphy *InstancePtr, XDphy_Config *CfgPtr, UINTPTR EffectiveAddr) |
Initialize the XDphy instance provided by the caller based on the given Config structure. More... | |
u32 | XDphy_Configure (XDphy *InstancePtr, u8 Handle, u32 Value) |
Configure the registers of the Dphy instance. More... | |
u8 | XDphy_GetRegIntfcPresent (XDphy *InstancePtr) |
Get if register interface is present from the config structure for specified DPHY instance. More... | |
u32 | XDphy_GetInfo (XDphy *InstancePtr, u8 Handle) |
Get information stored in the DPhy instance based on the handle passed. More... | |
void | XDphy_Reset (XDphy *InstancePtr) |
This is used to do a soft reset of the DPhy IP instance. More... | |
void | XDphy_ClearDataLane (XDphy *InstancePtr, u8 DataLane, u32 Mask) |
This is used to clear the Abort Error (Escape or High Speed) bits in the Data Lane 0 through 3. More... | |
u32 | XDphy_GetClkLaneStatus (XDphy *InstancePtr) |
This is used to get information about Clock Lane status. More... | |
u32 | XDphy_GetClkLaneMode (XDphy *InstancePtr) |
This is used to get specific Lane mode information about Clock Lane. More... | |
u32 | XDphy_GetDataLaneStatus (XDphy *InstancePtr, u8 DataLane) |
This is used to get information about a Data Lane status. More... | |
u8 | XDphy_GetDLCalibStatus (XDphy *InstancePtr, u8 DataLane) |
This is used to get Data Lane Calibration status. More... | |
u32 | XDphy_GetDataLaneMode (XDphy *InstancePtr, u8 DataLane) |
This is used to get specfic Lane mode information about a Data Lane. More... | |
u16 | XDphy_GetPacketCount (XDphy *InstancePtr, u8 DataLane) |
This is used to get count of packets received on each lane. More... | |
void | XDphy_Activate (XDphy *InstancePtr, u8 Flag) |
This function is used to enable or disable the DPhy core. More... | |
XDphy_Config * | XDphy_LookupConfig (u32 DeviceId) |
Look up the hardware configuration for a device instance. More... | |
u32 | XDphy_SelfTest (XDphy *InstancePtr) |
Runs a self-test on the driver/device. More... | |
DPHY Modes | |
#define | XDPHY_MODE_MIN 0 |
Lower limit for Mode. More... | |
#define | XDPHY_LOW_POWER_MODE 0 |
Lane in Low Power Mode. More... | |
#define | XDPHY_HIGH_POWER_MODE 1 |
Lane in High Power Mode. More... | |
#define | XDPHY_ESCAPE_MODE 2 |
Lane in Escape Mode. More... | |
#define | XDPHY_MODE_MAX 2 |
Upper Limit for mode. More... | |
#define | XDPHY_MAX_LANES_V10 4 |
V1.0 supports 4 Lanes. More... | |
DPHY Info Handles | |
#define | XDPHY_HANDLE_MIN 0 |
Lower Bound for XDPHY_HANDLE. More... | |
#define | XDPHY_HANDLE_IDELAY 0 |
Handle for IDELAY Reg. More... | |
#define | XDPHY_HANDLE_INIT_TIMER 1 |
Handle for Initialization Timer. More... | |
#define | XDPHY_HANDLE_WAKEUP 2 |
Handle for Wakeup timer. More... | |
#define | XDPHY_HANDLE_HSTIMEOUT 3 |
Handle for HS Timeout. More... | |
#define | XDPHY_HANDLE_ESCTIMEOUT 4 |
Handle for Escape Timeout. More... | |
#define | XDPHY_HANDLE_CLKLANE 5 |
Handle for Clock Lane. More... | |
#define | XDPHY_HANDLE_DLANE0 6 |
Handle for Data Lane 0. More... | |
#define | XDPHY_HANDLE_DLANE1 7 |
Handle for Data Lane 1. More... | |
#define | XDPHY_HANDLE_DLANE2 8 |
Handle for Data Lane 2. More... | |
#define | XDPHY_HANDLE_DLANE3 9 |
Handle for Data Lane 3. More... | |
#define | XDPHY_HANDLE_HSSETTLE 10 |
Handle for HS SETTLE. More... | |
#define | XDPHY_HANDLE_DLANE4 11 |
Handle for Data Lane 4. More... | |
#define | XDPHY_HANDLE_DLANE5 12 |
Handle for Data Lane 5. More... | |
#define | XDPHY_HANDLE_DLANE6 13 |
Handle for Data Lane 6. More... | |
#define | XDPHY_HANDLE_DLANE7 14 |
Handle for Data Lane 7. More... | |
#define | XDPHY_HANDLE_HSSETTLE1 15 |
Handle for HS SETTLE L1. More... | |
#define | XDPHY_HANDLE_HSSETTLE2 16 |
Handle for HS SETTLE L2. More... | |
#define | XDPHY_HANDLE_HSSETTLE3 17 |
Handle for HS SETTLE L3. More... | |
#define | XDPHY_HANDLE_HSSETTLE4 18 |
Handle for HS SETTLE. More... | |
#define | XDPHY_HANDLE_HSSETTLE5 19 |
Handle for HS SETTLE L1. More... | |
#define | XDPHY_HANDLE_HSSETTLE6 20 |
Handle for HS SETTLE L2. More... | |
#define | XDPHY_HANDLE_HSSETTLE7 21 |
Handle for HS SETTLE L3. More... | |
#define | XDPHY_HANDLE_MAX 21 |
Upper Bound for XDPHY_HANDLE. More... | |
DPHY HSTIMEOUT range | |
#define | XDPHY_HS_TIMEOUT_MIN_VALUE 10000UL |
#define | XDPHY_HS_TIMEOUT_MAX_VALUE 65541UL |
DPHY HSSETTLE range | |
#define | XDPHY_HS_SETTLE_MAX_VALUE 0x1FF |
DPHY Flags to Enable or Disable core | |
#define | XDPHY_ENABLE_FLAG 1 |
#define | XDPHY_DISABLE_FLAG 0 |
#define XDPHY_ESCAPE_MODE 2 |
Lane in Escape Mode.
#define XDPHY_H_ |
Prevent circular inclusions by using protection macros.
#define XDPHY_HANDLE_CLKLANE 5 |
Handle for Clock Lane.
Referenced by XDphy_Configure(), and XDphy_GetInfo().
#define XDPHY_HANDLE_DLANE0 6 |
Handle for Data Lane 0.
Referenced by XDphy_Configure(), and XDphy_GetInfo().
#define XDPHY_HANDLE_DLANE1 7 |
Handle for Data Lane 1.
Referenced by XDphy_Configure(), and XDphy_GetInfo().
#define XDPHY_HANDLE_DLANE2 8 |
Handle for Data Lane 2.
Referenced by XDphy_Configure(), and XDphy_GetInfo().
#define XDPHY_HANDLE_DLANE3 9 |
Handle for Data Lane 3.
Referenced by XDphy_Configure(), and XDphy_GetInfo().
#define XDPHY_HANDLE_DLANE4 11 |
Handle for Data Lane 4.
Referenced by XDphy_Configure(), and XDphy_GetInfo().
#define XDPHY_HANDLE_DLANE5 12 |
Handle for Data Lane 5.
Referenced by XDphy_Configure(), and XDphy_GetInfo().
#define XDPHY_HANDLE_DLANE6 13 |
Handle for Data Lane 6.
Referenced by XDphy_Configure(), and XDphy_GetInfo().
#define XDPHY_HANDLE_DLANE7 14 |
Handle for Data Lane 7.
Referenced by XDphy_Configure(), and XDphy_GetInfo().
#define XDPHY_HANDLE_ESCTIMEOUT 4 |
Handle for Escape Timeout.
Referenced by XDphy_Configure(), and XDphy_GetInfo().
#define XDPHY_HANDLE_HSSETTLE 10 |
Handle for HS SETTLE.
Referenced by XDphy_Configure(), and XDphy_GetInfo().
#define XDPHY_HANDLE_HSSETTLE1 15 |
Handle for HS SETTLE L1.
Referenced by XDphy_Configure(), and XDphy_GetInfo().
#define XDPHY_HANDLE_HSSETTLE2 16 |
Handle for HS SETTLE L2.
Referenced by XDphy_Configure(), and XDphy_GetInfo().
#define XDPHY_HANDLE_HSSETTLE3 17 |
Handle for HS SETTLE L3.
Referenced by XDphy_Configure(), and XDphy_GetInfo().
#define XDPHY_HANDLE_HSSETTLE4 18 |
Handle for HS SETTLE.
Referenced by XDphy_Configure(), and XDphy_GetInfo().
#define XDPHY_HANDLE_HSSETTLE5 19 |
Handle for HS SETTLE L1.
Referenced by XDphy_Configure(), and XDphy_GetInfo().
#define XDPHY_HANDLE_HSSETTLE6 20 |
Handle for HS SETTLE L2.
Referenced by XDphy_Configure(), and XDphy_GetInfo().
#define XDPHY_HANDLE_HSSETTLE7 21 |
Handle for HS SETTLE L3.
Referenced by XDphy_Configure(), and XDphy_GetInfo().
#define XDPHY_HANDLE_HSTIMEOUT 3 |
Handle for HS Timeout.
Referenced by XDphy_Configure(), XDphy_GetInfo(), and XDphy_SelfTest().
#define XDPHY_HANDLE_IDELAY 0 |
Handle for IDELAY Reg.
Referenced by XDphy_Configure(), and XDphy_GetInfo().
#define XDPHY_HANDLE_INIT_TIMER 1 |
Handle for Initialization Timer.
Referenced by XDphy_Configure(), and XDphy_GetInfo().
#define XDPHY_HANDLE_MAX 21 |
Upper Bound for XDPHY_HANDLE.
Referenced by XDphy_Configure(), and XDphy_GetInfo().
#define XDPHY_HANDLE_MIN 0 |
Lower Bound for XDPHY_HANDLE.
#define XDPHY_HANDLE_WAKEUP 2 |
Handle for Wakeup timer.
Referenced by XDphy_Configure(), and XDphy_GetInfo().
#define XDPHY_HIGH_POWER_MODE 1 |
Lane in High Power Mode.
#define XDPHY_LOW_POWER_MODE 0 |
Lane in Low Power Mode.
#define XDPHY_MAX_LANES_V10 4 |
V1.0 supports 4 Lanes.
Referenced by XDphy_Configure(), and XDphy_GetInfo().
#define XDPHY_MODE_MAX 2 |
Upper Limit for mode.
#define XDPHY_MODE_MIN 0 |
Lower limit for Mode.
void XDphy_Activate | ( | XDphy * | InstancePtr, |
u8 | Flag | ||
) |
This function is used to enable or disable the DPhy core.
InstancePtr | is the XDphy instance to operate on. |
Flag | denoting whether to enable or disable the DPhy core |
References XDphy_Config::BaseAddr, XDphy::Config, XDphy_Config::IsRegisterPresent, XDPHY_CTRL_REG_DPHYEN_MASK, and XDPHY_CTRL_REG_OFFSET.
u32 XDphy_CfgInitialize | ( | XDphy * | InstancePtr, |
XDphy_Config * | CfgPtr, | ||
UINTPTR | EffectiveAddr | ||
) |
Initialize the XDphy instance provided by the caller based on the given Config structure.
InstancePtr | is the XDphy instance to operate on. |
CfgPtr | is the device configuration structure containing information about a specific DPhy instance. |
EffectiveAddr | is the base address of the device. If address translation is being used, then this parameter must reflect the virtual base address. Otherwise, the physical address should be used. |
References XDphy_Config::BaseAddr, XDphy::Config, and XDphy::IsReady.
Referenced by DphySelfTestExample().
void XDphy_ClearDataLane | ( | XDphy * | InstancePtr, |
u8 | DataLane, | ||
u32 | Mask | ||
) |
This is used to clear the Abort Error (Escape or High Speed) bits in the Data Lane 0 through 3.
InstancePtr | is the XDphy instance to operate on. |
DataLane | represents which Data Lane to act upon |
Mask | contains information about which bits to reset |
References XDphy_Config::BaseAddr, XDphy::Config, XDphy_Config::IsRegisterPresent, XDPHY_DL0STATUS_REG_OFFSET, XDPHY_DLXSTATUS_REG_ESCABRT_MASK, and XDPHY_DLXSTATUS_REG_HSABRT_MASK.
u32 XDphy_Configure | ( | XDphy * | InstancePtr, |
u8 | Handle, | ||
u32 | Value | ||
) |
Configure the registers of the Dphy instance.
InstancePtr | is the XDphy instance to operate on. |
Handle | to one of the registers to be configured |
Value | to be set for the particular Handle of the DPHY instance |
References XDphy::Config, XDphy_Config::EnableTimeOutRegs, XDphy_Config::IsRegisterPresent, XDphy_Config::IsRx, XDphy_Config::MaxLanesPresent, XDPHY_ESCTIMEOUT_REG_OFFSET, XDPHY_HANDLE_CLKLANE, XDPHY_HANDLE_DLANE0, XDPHY_HANDLE_DLANE1, XDPHY_HANDLE_DLANE2, XDPHY_HANDLE_DLANE3, XDPHY_HANDLE_DLANE4, XDPHY_HANDLE_DLANE5, XDPHY_HANDLE_DLANE6, XDPHY_HANDLE_DLANE7, XDPHY_HANDLE_ESCTIMEOUT, XDPHY_HANDLE_HSSETTLE, XDPHY_HANDLE_HSSETTLE1, XDPHY_HANDLE_HSSETTLE2, XDPHY_HANDLE_HSSETTLE3, XDPHY_HANDLE_HSSETTLE4, XDPHY_HANDLE_HSSETTLE5, XDPHY_HANDLE_HSSETTLE6, XDPHY_HANDLE_HSSETTLE7, XDPHY_HANDLE_HSTIMEOUT, XDPHY_HANDLE_IDELAY, XDPHY_HANDLE_INIT_TIMER, XDPHY_HANDLE_MAX, XDPHY_HANDLE_WAKEUP, XDPHY_HSEXIT_IDELAY_REG_OFFSET, XDPHY_HSEXIT_IDELAY_REG_TAP_MASK, XDPHY_HSSETTLE1_REG_OFFSET, XDPHY_HSSETTLE2_REG_OFFSET, XDPHY_HSSETTLE3_REG_OFFSET, XDPHY_HSSETTLE4_REG_OFFSET, XDPHY_HSSETTLE5_REG_OFFSET, XDPHY_HSSETTLE6_REG_OFFSET, XDPHY_HSSETTLE7_REG_OFFSET, XDPHY_HSSETTLE_REG_OFFSET, XDPHY_HSTIMEOUT_REG_OFFSET, XDPHY_IDELAY58_REG_OFFSET, XDPHY_INIT_REG_OFFSET, XDPHY_MAX_LANES_V10, and XDPHY_WAKEUP_REG_OFFSET.
u32 XDphy_GetClkLaneMode | ( | XDphy * | InstancePtr | ) |
This is used to get specific Lane mode information about Clock Lane.
InstancePtr | is the XDphy instance to operate on. |
References XDphy::Config, XDphy_Config::IsRegisterPresent, XDPHY_CLSTATUS_REG_MODE_MASK, and XDphy_GetClkLaneStatus().
u32 XDphy_GetClkLaneStatus | ( | XDphy * | InstancePtr | ) |
This is used to get information about Clock Lane status.
InstancePtr | is the XDphy instance to operate on. |
References XDphy_Config::BaseAddr, XDphy::Config, XDphy_Config::IsRegisterPresent, and XDPHY_CLSTATUS_REG_OFFSET.
Referenced by XDphy_GetClkLaneMode().
u32 XDphy_GetDataLaneMode | ( | XDphy * | InstancePtr, |
u8 | DataLane | ||
) |
This is used to get specfic Lane mode information about a Data Lane.
InstancePtr | is the XDphy instance to operate on. |
DataLane | for which the mode info is requested. |
References XDphy::Config, XDphy_Config::IsRegisterPresent, XDPHY_DLXSTATUS_REG_MODE_MASK, and XDphy_GetDataLaneStatus().
u32 XDphy_GetDataLaneStatus | ( | XDphy * | InstancePtr, |
u8 | DataLane | ||
) |
This is used to get information about a Data Lane status.
InstancePtr | is the XDphy instance to operate on. |
DataLane | for which the status is sought for. |
References XDphy_Config::BaseAddr, XDphy::Config, XDphy_Config::IsRegisterPresent, and XDPHY_DL0STATUS_REG_OFFSET.
Referenced by XDphy_GetDataLaneMode().
u8 XDphy_GetDLCalibStatus | ( | XDphy * | InstancePtr, |
u8 | DataLane | ||
) |
This is used to get Data Lane Calibration status.
InstancePtr | is the XDphy instance to operate on. |
DataLane | for which the calib status is sought for. |
References XDphy_Config::BaseAddr, XDphy::Config, XDphy_Config::IsRegisterPresent, XDPHY_DL0STATUS_REG_OFFSET, XDPHY_DLXSTATUS_REG_CALIB_COMPLETE_MASK, and XDPHY_DLXSTATUS_REG_CALIB_STATUS_MASK.
u32 XDphy_GetInfo | ( | XDphy * | InstancePtr, |
u8 | Handle | ||
) |
Get information stored in the DPhy instance based on the handle passed.
InstancePtr | is the XDphy instance to operate on. |
Handle | to one of the registers to be configured |
References XDphy::Config, XDphy_Config::EnableTimeOutRegs, XDphy_Config::EscTimeout, XDphy_Config::HSTimeOut, XDphy_Config::IsRegisterPresent, XDphy_Config::IsRx, XDphy_Config::MaxLanesPresent, XDPHY_CLSTATUS_REG_OFFSET, XDPHY_DL0STATUS_REG_OFFSET, XDPHY_DL1STATUS_REG_OFFSET, XDPHY_DL2STATUS_REG_OFFSET, XDPHY_DL3STATUS_REG_OFFSET, XDPHY_DL4STATUS_REG_OFFSET, XDPHY_DL5STATUS_REG_OFFSET, XDPHY_DL6STATUS_REG_OFFSET, XDPHY_DL7STATUS_REG_OFFSET, XDPHY_ESCTIMEOUT_REG_OFFSET, XDPHY_HANDLE_CLKLANE, XDPHY_HANDLE_DLANE0, XDPHY_HANDLE_DLANE1, XDPHY_HANDLE_DLANE2, XDPHY_HANDLE_DLANE3, XDPHY_HANDLE_DLANE4, XDPHY_HANDLE_DLANE5, XDPHY_HANDLE_DLANE6, XDPHY_HANDLE_DLANE7, XDPHY_HANDLE_ESCTIMEOUT, XDPHY_HANDLE_HSSETTLE, XDPHY_HANDLE_HSSETTLE1, XDPHY_HANDLE_HSSETTLE2, XDPHY_HANDLE_HSSETTLE3, XDPHY_HANDLE_HSSETTLE4, XDPHY_HANDLE_HSSETTLE5, XDPHY_HANDLE_HSSETTLE6, XDPHY_HANDLE_HSSETTLE7, XDPHY_HANDLE_HSTIMEOUT, XDPHY_HANDLE_IDELAY, XDPHY_HANDLE_INIT_TIMER, XDPHY_HANDLE_MAX, XDPHY_HANDLE_WAKEUP, XDPHY_HSEXIT_IDELAY_REG_OFFSET, XDPHY_HSSETTLE1_REG_OFFSET, XDPHY_HSSETTLE2_REG_OFFSET, XDPHY_HSSETTLE3_REG_OFFSET, XDPHY_HSSETTLE4_REG_OFFSET, XDPHY_HSSETTLE5_REG_OFFSET, XDPHY_HSSETTLE6_REG_OFFSET, XDPHY_HSSETTLE7_REG_OFFSET, XDPHY_HSSETTLE_REG_OFFSET, XDPHY_HSTIMEOUT_REG_OFFSET, XDPHY_INIT_REG_OFFSET, XDPHY_MAX_LANES_V10, and XDPHY_WAKEUP_REG_OFFSET.
Referenced by XDphy_SelfTest().
u16 XDphy_GetPacketCount | ( | XDphy * | InstancePtr, |
u8 | DataLane | ||
) |
This is used to get count of packets received on each lane.
InstancePtr | is the XDphy instance to operate on. |
DataLane | for which the mode info is requested. |
References XDphy_Config::BaseAddr, XDphy::Config, XDphy_Config::IsRegisterPresent, XDPHY_DL0STATUS_REG_OFFSET, XDPHY_DLXSTATUS_REG_PACKCOUNT_OFFSET, and XDPHY_DLXSTATUS_REG_PACKETCOUNT_MASK.
u8 XDphy_GetRegIntfcPresent | ( | XDphy * | InstancePtr | ) |
Get if register interface is present from the config structure for specified DPHY instance.
InstancePtr | is the XDphy instance to operate on. |
References XDphy::Config, and XDphy_Config::IsRegisterPresent.
Referenced by DphySelfTestExample().
XDphy_Config * XDphy_LookupConfig | ( | u32 | DeviceId | ) |
Look up the hardware configuration for a device instance.
DeviceId | is the unique device ID of the device to lookup for |
Referenced by DphySelfTestExample().
void XDphy_Reset | ( | XDphy * | InstancePtr | ) |
This is used to do a soft reset of the DPhy IP instance.
The reset takes approx 20 core clock cycles to become effective.
InstancePtr | is the XDphy instance to operate on. |
References XDphy::Config, XDphy::IsReady, XDphy_Config::IsRegisterPresent, XDPHY_CTRL_REG_OFFSET, and XDPHY_CTRL_REG_SOFTRESET_MASK.
u32 XDphy_SelfTest | ( | XDphy * | InstancePtr | ) |
Runs a self-test on the driver/device.
This test checks if HS Timeout value present in register matches the one from the generated file.
InstancePtr | is a pointer to the XDphy instance. |
References XDphy::Config, XDphy_Config::HSTimeOut, XDphy_GetInfo(), and XDPHY_HANDLE_HSTIMEOUT.
Referenced by DphySelfTestExample().