xdprxss.c File Reference

#include "xdprxss.h"
#include "xdprxss_mcdp6000.h"
#include "string.h"
#include "xdebug.h"
#include "sleep.h"

Macros
#define	EDID_IIC_ADDRESS   0x50
	EDID IIC slave address. More...
#define	XCLK_WIZ_PRIM_L_OFFSET   0x000003B0
	Clock Wizard primary low offset. More...
#define	XCLK_WIZ_PRIM_H_OFFSET   0x000003B4
	Clock Wizard primary high offset. More...
#define	XCLK_WIZ_SEC_L_OFFSET   0x000003B8
	Clock Wizard secondary low offset. More...
#define	XCLK_WIZ_SEC_H_OFFSET   0x000003BC
	Clock Wizard secondary high offset. More...
#define	XCLK_WIZ_STATUS_RETRY   10000
	Max retries for clock lock status. More...
#define	XCLK_WIZ_STATUS_WAIT   100
	Wait time in microseconds between retries. More...
Clock Wizard register offsets and default values
#define	XCLK_WIZ_SWRST_OFFSET   0x00000000
	Software reset offset. More...
#define	XCLK_WIZ_SWRST_VAL   0x0A
	Software reset value. More...
#define	XCLK_WIZ_STATUS_OFFSET   0x00000004
	Status register offset. More...
#define	XCLK_WIZ_ISR_OFFSET   0x0000000C
	Interrupt status register offset. More...
#define	XCLK_WIZ_IER_OFFSET   0x00000010
	Interrupt enable register offset. More...
#define	XCLK_WIZ_RECONFIG_OFFSET   0x00000014
	Reconfiguration register offset. More...
#define	XCLK_WIZ_RECONFIG_VAL   0x03
	Reconfiguration trigger value. More...
#define	XCLK_WIZ_REG1_OFFSET   0x00000330
	ClkOut0 register 1 offset. More...
#define	XCLK_WIZ_REG2_OFFSET   0x00000334
	ClkOut0 register 2 offset. More...
#define	XCLK_WIZ_REG3_OFFSET   0x00000338
	ClkOut0 register 3 offset. More...
#define	XCLK_WIZ_REG4_OFFSET   0x0000033C
	ClkOut0 register 4 offset. More...
#define	XCLK_WIZ_REG12_OFFSET   0x00000380
	Divider register offset. More...
#define	XCLK_WIZ_REG13_OFFSET   0x00000384
	Divider register 2 offset. More...
#define	XCLK_WIZ_REG11_OFFSET   0x00000378
	ClkOut0 register 11 offset. More...
#define	XCLK_WIZ_REG11_VAL   0x2E
	ClkOut0 register 11 default value. More...
#define	XCLK_WIZ_REG14_OFFSET   0x00000398
	Filter register offset. More...
#define	XCLK_WIZ_REG14_VAL   0xE80
	Filter register default value. More...
#define	XCLK_WIZ_REG15_OFFSET   0x0000039C
	Lock register 1 offset. More...
#define	XCLK_WIZ_REG15_VAL   0x4271
	Lock register 1 default value. More...
#define	XCLK_WIZ_REG16_OFFSET   0x000003A0
	Lock register 2 offset. More...
#define	XCLK_WIZ_REG16_VAL   0x43E9
	Lock register 2 default value. More...
#define	XCLK_WIZ_REG17_OFFSET   0x000003A8
	Lock register 3 offset. More...
#define	XCLK_WIZ_REG17_VAL   0x1C
	Lock register 3 default value. More...
#define	XCLK_WIZ_REG19_OFFSET   0x000003CC
	Power register offset. More...
#define	XCLK_WIZ_REG25_OFFSET   0x000003F0
	FBout register offset. More...
#define	XCLK_WIZ_REG26_OFFSET   0x000003FC
	FBout register 2 offset. More...
#define	XCLK_WIZ_REG26_VAL   0x01
	FBout register 2 default value. More...
CLKx5 Wizard per-link-rate configuration values
#define	XCLK_WIZ_REG2_810GBPS_CFG_VAL   0x0E0E
	8.1 Gbps configuration values More...
#define	XCLK_WIZ_REG3_810GBPS_CFG_VAL   0xBB00
	Reg3 config for 8.1 Gbps. More...
#define	XCLK_WIZ_REG4_810GBPS_CFG_VAL   0x0101
	Reg4 config for 8.1 Gbps. More...
#define	XCLK_WIZ_REG11_810GBPS_CFG_VAL   0x002E
	Reg11 config for 8.1 Gbps. More...
#define	XCLK_WIZ_REG15_810GBPS_CFG_VAL   0x420D
	Reg15 config for 8.1 Gbps. More...
#define	XCLK_WIZ_REG17_810GBPS_CFG_VAL   0x0002
	Reg17 config for 8.1 Gbps. More...
#define	XCLK_WIZ_PRIM_L_810GBPS_CFG_VAL   0xB98A
	Primary low config for 8.1 Gbps. More...
#define	XCLK_WIZ_PRIM_H_810GBPS_CFG_VAL   0x0007
	Primary high config for 8.1 Gbps. More...
#define	XCLK_WIZ_SEC_L_810GBPS_CFG_VAL   0xDCC5
	Secondary low config for 8.1 Gbps. More...
#define	XCLK_WIZ_SEC_H_810GBPS_CFG_VAL   0x0003
	Secondary high config for 8.1 Gbps. More...
#define	XCLK_WIZ_REG2_540GBPS_CFG_VAL   0x1616
	5.4 Gbps configuration values More...
#define	XCLK_WIZ_REG3_540GBPS_CFG_VAL   0xBB00
	Reg3 config for 5.4 Gbps. More...
#define	XCLK_WIZ_REG4_540GBPS_CFG_VAL   0x0202
	Reg4 config for 5.4 Gbps. More...
#define	XCLK_WIZ_REG11_540GBPS_CFG_VAL   0x002F
	Reg11 config for 5.4 Gbps. More...
#define	XCLK_WIZ_REG15_540GBPS_CFG_VAL   0x412C
	Reg15 config for 5.4 Gbps. More...
#define	XCLK_WIZ_REG17_540GBPS_CFG_VAL   0x000C
	Reg17 config for 5.4 Gbps. More...
#define	XCLK_WIZ_PRIM_L_540GBPS_CFG_VAL   0x265C
	Primary low config for 5.4 Gbps. More...
#define	XCLK_WIZ_PRIM_H_540GBPS_CFG_VAL   0x0005
	Primary high config for 5.4 Gbps. More...
#define	XCLK_WIZ_SEC_L_540GBPS_CFG_VAL   0x932E
	Secondary low config for 5.4 Gbps. More...
#define	XCLK_WIZ_SEC_H_540GBPS_CFG_VAL   0x0002
	Secondary high config for 5.4 Gbps. More...
#define	XCLK_WIZ_REG2_270GBPS_CFG_VAL   0x2C2C
	2.7 Gbps configuration values More...
#define	XCLK_WIZ_REG3_270GBPS_CFG_VAL   0x1B00
	Reg3 config for 2.7 Gbps. More...
#define	XCLK_WIZ_REG4_270GBPS_CFG_VAL   0x0505
	Reg4 config for 2.7 Gbps. More...
#define	XCLK_WIZ_REG11_270GBPS_CFG_VAL   0x002E
	Reg11 config for 2.7 Gbps. More...
#define	XCLK_WIZ_REG15_270GBPS_CFG_VAL   0x40FA
	Reg15 config for 2.7 Gbps. More...
#define	XCLK_WIZ_REG17_270GBPS_CFG_VAL   0x0004
	Reg17 config for 2.7 Gbps. More...
#define	XCLK_WIZ_PRIM_L_270GBPS_CFG_VAL   0x932E
	Primary low config for 2.7 Gbps. More...
#define	XCLK_WIZ_PRIM_H_270GBPS_CFG_VAL   0x0002
	Primary high config for 2.7 Gbps. More...
#define	XCLK_WIZ_SEC_L_270GBPS_CFG_VAL   0x86A0
	Secondary low config for 2.7 Gbps. More...
#define	XCLK_WIZ_SEC_H_270GBPS_CFG_VAL   0x0001
	Secondary high config for 2.7 Gbps. More...
#define	XCLK_WIZ_REG2_162GBPS_CFG_VAL   0x4A4A
	1.62 Gbps configuration values More...
#define	XCLK_WIZ_REG3_162GBPS_CFG_VAL   0xBA00
	Reg3 config for 1.62 Gbps. More...
#define	XCLK_WIZ_REG4_162GBPS_CFG_VAL   0x0909
	Reg4 config for 1.62 Gbps. More...
#define	XCLK_WIZ_REG11_162GBPS_CFG_VAL   0x002C
	Reg11 config for 1.62 Gbps. More...
#define	XCLK_WIZ_REG15_162GBPS_CFG_VAL   0x40FA
	Reg15 config for 1.62 Gbps. More...
#define	XCLK_WIZ_REG17_162GBPS_CFG_VAL   0x0008
	Reg17 config for 1.62 Gbps. More...
#define	XCLK_WIZ_PRIM_L_162GBPS_CFG_VAL   0x8B82
	Primary low config for 1.62 Gbps. More...
#define	XCLK_WIZ_PRIM_H_162GBPS_CFG_VAL   0x0001
	Primary high config for 1.62 Gbps. More...
#define	XCLK_WIZ_SEC_L_162GBPS_CFG_VAL   0x86A0
	Secondary low config for 1.62 Gbps. More...
#define	XCLK_WIZ_SEC_H_162GBPS_CFG_VAL   0x0001
	Secondary high config for 1.62 Gbps. More...
Clock Wizard control bit masks and shift values
#define	XCLK_WIZ_LOCK   1
	Clock lock status bit. More...
#define	XCLK_WIZ_REG3_PREDIV2   (1 << 11)
	ClkOut0 reg3 pre-divide by 2. More...
#define	XCLK_WIZ_REG3_USED   (1 << 12)
	ClkOut0 reg3 used bit. More...
#define	XCLK_WIZ_REG3_MX   (1 << 9)
	ClkOut0 reg3 MX bit. More...
#define	XCLK_WIZ_REG1_PREDIV2   (1 << 12)
	FBout reg1 pre-divide by 2. More...
#define	XCLK_WIZ_REG1_EN   (1 << 9)
	FBout enable bit. More...
#define	XCLK_WIZ_REG1_MX   (1 << 10)
	FBout MX bit. More...
#define	XCLK_WIZ_RECONFIG_LOAD   1
	Reconfiguration load trigger. More...
#define	XCLK_WIZ_RECONFIG_SADDR   2
	Reconfiguration start address. More...
#define	XCLK_WIZ_REG1_EDGE_MASK   (1 << 8)
	FBout reg1 edge mask. More...
#define	XCLK_WIZ_CLKOUT0_PREDIV2_SHIFT   11
	ClkOut0 pre-divide by 2 shift. More...
#define	XCLK_WIZ_CLKOUT0_MX_SHIFT   9
	ClkOut0 MX shift. More...
#define	XCLK_WIZ_CLKOUT0_P5EN_SHIFT   13
	ClkOut0 phase5 enable shift. More...
#define	XCLK_WIZ_CLKOUT0_P5FEDGE_SHIFT   15
	ClkOut0 phase5 falling edge shift. More...
#define	XCLK_WIZ_REG12_EDGE_SHIFT   10
	Divider edge shift. More...
MMCM multiplier and divider values
#define	M_VAL_405   28
	MMCM multiplier for 405 MHz (8.1 Gbps link rate) More...
#define	M_VAL_270   44
	MMCM multiplier for 270 MHz (5.4 Gbps link rate) More...
#define	M_VAL_135   88
	MMCM multiplier for 135 MHz (2.7 Gbps link rate) More...
#define	M_VAL_81   148
	MMCM multiplier for 81 MHz (1.62 Gbps link rate) More...
#define	D_VAL_ALL   5
	MMCM divider value for all link rates. More...

Functions
u32	XDpRxSs_CfgInitialize (XDpRxSs *InstancePtr, XDpRxSs_Config *CfgPtr, UINTPTR EffectiveAddr)
	This function initializes the DisplayPort Receiver Subsystem core. More...
void	XDpRxSs_Reset (XDpRxSs *InstancePtr)
	This function resets the DisplayPort Receiver Subsystem including all sub-cores. More...
u32	XDpRxSs_Start (XDpRxSs *InstancePtr)
	This function starts the DisplayPort Receiver Subsystem including all sub-cores. More...
u32	XDpRxSs_SetLinkRate (XDpRxSs *InstancePtr, u8 LinkRate)
	This function sets the data rate to be used by the DisplayPort RX Subsystem core. More...
u32	XDpRxSs_SetLaneCount (XDpRxSs *InstancePtr, u8 LaneCount)
	This function sets the number of lanes to be used by DisplayPort RX Subsystem core. More...
u32	XDpRxSs_ExposePort (XDpRxSs *InstancePtr, u8 Port)
	This function allows the user to select number of ports to be exposed when replying to a LINK_ADDRESS sideband message and hides rest of the ports. More...
u32	XDpRxSs_CheckLinkStatus (XDpRxSs *InstancePtr)
	This function checks if the receiver's DisplayPort Configuration Data (DPCD) indicates that the receiver has achieved clock recovery, channel equalization, symbol lock, and interlane alignment for all lanes currently in use. More...
void	XDpRxSs_SetUserPixelWidth (XDpRxSs *InstancePtr, u8 UserPixelWidth)
	This function configures the number of pixels output through the user data interface. More...
u8	XDpRxss_GetBpc (XDpRxSs *InstancePtr, u8 Stream)
	This function extracts the bits per color from MISC0 or VSC SDP packet based on whether reception of colorimetry information through VSC SDP packets or through MISC registers of the stream. More...
u8	XDpRxss_GetColorComponent (XDpRxSs *InstancePtr, u8 Stream)
	This function extracts the color component format from MISC0 or VSC SDP packet based on whether reception of colorimetry information through VSC SDP packets or through MISC registers of the stream. More...
u8	XDpRxss_GetColorimetry (XDpRxSs *InstancePtr, u8 Stream)
	This function extracts the YCbCrColorimetry from MISC0 or VSC SDP packet based on whether reception of colorimetry information through VSC SDP packets or through MISC registers of the stream. More...
u8	XDpRxss_GetDynamicRange (XDpRxSs *InstancePtr, u8 Stream)
	This function extracts the dynamic range from MISC0 or VSC SDP packet based on whether reception of colorimetry information through VSC SDP packets or through MISC registers of the stream. More...
u32	XDpRxSs_HandleDownReq (XDpRxSs *InstancePtr)
	This function handles incoming sideband messages. More...
void	XDpRxSs_McDp6000_init (void *InstancePtr)
	This routine initializes the MCDP6000 part on the VFMC card used for DP 1.4. More...
void	XDpRxSs_SetAdaptiveSyncCaps (XDpRxSs *InstancePtr, u32 Enable)
	This function sets Adaptive-Sync capabilities to DisplayPort RX Subsystem. More...
void	XDpRxSs_MaskAdaptiveIntr (XDpRxSs *InstancePtr, u32 Mask)
	This function masks the Adaptive-Sync interrupts from DisplayPort RX Subsystem. More...
void	XDpRxSs_UnMaskAdaptiveIntr (XDpRxSs *InstancePtr, u32 Mask)
	This function unmasks Adaptive-Sync interrupt from DisplayPort RX Subsystem. More...
int	XDpRxSs_GetVblank (XDpRxSs *InstancePtr, u8 Stream)
	This function retrieves the current vblank value of the incoming video stream. More...
int	XDpRxSs_GetVtotal (XDpRxSs *InstancePtr, u8 Stream)
	This function retrieves the current VTotal value of the incoming video stream. More...
int	XDpRxSs_Get_Dec_Clk_Lock (XDpRxSs *InstancePtr)
	This function resets the Clock Wizard and waits for it to lock after the receiver decode clock has been reconfigured. More...

Variables
u8	GenEdid [128]
	A generic EDID (Extended Display Identification Data) structure. More...
u8	GenDpcd []
	A generic DPCD (DisplayPort Configuration Data) structure. More...
XDpRxSs_SubCores	DpRxSsSubCores [XPAR_XDPRXSS_NUM_INSTANCES]
	DisplayPort RX subcores instance array. More...