Data Structures
struct	XDpRxSs_UsrOpt
	User input structure. More...

struct	XDpRxSs_DpSubCore
	DisplayPort Sub-core structure. More...

struct	XDpRxSs_IicSubCore
	IIC Sub-core structure. More...

struct	XDpRxSs_SubCoreConfig
	This typedef contains configuration information for the DpRxSs subcore instances. More...

struct	XDpRxSs_Hdcp1xSubCore
	High-Bandwidth Content Protection (HDCP) Sub-core structure. More...

struct	XDpRxSs_TmrCtrSubCore
	Timer Counter Sub-core structure. More...

struct	XDpRxSs_Hdcp22SubCore
	Sub-Core Configuration Table. More...

struct	XDpRxSs_Config
	This typedef contains configuration information for the DisplayPort Receiver Subsystem core. More...

struct	XDpRxSs
	The DisplayPort RX Subsystem driver instance data. More...

Macros
#define	EDID_IIC_ADDRESS 0x50
	EDID IIC slave address. More...

#define	XCLK_WIZ_PRIM_L_OFFSET 0x000003B0
	Clock Wizard primary low offset. More...

#define	XCLK_WIZ_PRIM_H_OFFSET 0x000003B4
	Clock Wizard primary high offset. More...

#define	XCLK_WIZ_SEC_L_OFFSET 0x000003B8
	Clock Wizard secondary low offset. More...

#define	XCLK_WIZ_SEC_H_OFFSET 0x000003BC
	Clock Wizard secondary high offset. More...

#define	XCLK_WIZ_STATUS_RETRY 10000
	Max retries for clock lock status. More...

#define	XCLK_WIZ_STATUS_WAIT 100
	Wait time in microseconds between retries. More...

#define	XDPRXSS_H_
	Prevent circular inclusions by using protection macros. More...

#define	XDpRxSs_TimerHandler XDp_TimerHandler
	Callback type which represents a custom timer wait handler. More...

#define	XDpRxSs_DtgEnable(InstancePtr) XDp_RxDtgEn((InstancePtr)->DpPtr)
	This function macro enables the display timing generator (DTG). More...

#define	XDpRxSs_DtgDisable(InstancePtr) XDp_RxDtgDis((InstancePtr)->DpPtr)
	This function macro disables the display timing generator (DTG). More...

#define	XDpRxSs_AudioEnable(InstancePtr) XDp_RxAudioEn((InstancePtr)->DpPtr)
	This function macro enables audio stream packets on the main link. More...

#define	XDpRxSs_AudioDisable(InstancePtr) XDp_RxAudioDis((InstancePtr)->DpPtr)
	This function macro disables audio stream packets on the main link. More...

#define	XDpRxSs_AudioReset(InstancePtr) XDp_RxAudioReset((InstancePtr)->DpPtr)
	This function macro resets the reception of audio stream packets on the main link. More...

#define	XDpRxSs_Mst_AudioEnable(InstancePtr, StreamId) XDp_Rx_Mst_AudioEn((InstancePtr)->DpPtr, StreamId)
	This function macro enables MST audio on a given stream on the main link. More...

#define	XDpRxSs_Mst_AudioDisable(InstancePtr) XDp_RxAudioDis((InstancePtr)->DpPtr)
	This function macro disables audio on a given stream on the main link. More...

#define	XDpRxSs_WaitUs(InstancePtr, MicroSeconds) XDp_WaitUs((InstancePtr)->DpPtr, MicroSeconds)
	This function macro is the delay/sleep function for the XDpRxSs driver. More...

#define	XDPRXSS_HW_H_
	Prevent circular inclusions by using protection macros. More...

#define	XDPRXSS_LINK_BW_SET_162GBPS XDP_RX_OVER_LINK_BW_SET_162GBPS
	1.62 Gbps link rate. More...

#define	XDPRXSS_LINK_BW_SET_270GBPS XDP_RX_OVER_LINK_BW_SET_270GBPS
	2.70 Gbps link rate. More...

#define	XDPRXSS_LINK_BW_SET_540GBPS XDP_RX_OVER_LINK_BW_SET_540GBPS
	5.40 Gbps link rate. More...

#define	XDPRXSS_LINK_BW_SET_810GBPS XDP_RX_OVER_LINK_BW_SET_810GBPS
	8.10 Gbps link rate. More...

#define	XDPRXSS_LANE_COUNT_SET_1 XDP_RX_OVER_LANE_COUNT_SET_1
	Lane count of 1. More...

#define	XDPRXSS_LANE_COUNT_SET_2 XDP_RX_OVER_LANE_COUNT_SET_2
	Lane count of 2. More...

#define	XDPRXSS_LANE_COUNT_SET_4 XDP_RX_OVER_LANE_COUNT_SET_4
	Lane count of 4. More...

#define	XDPRXSS_RX_PHY_CONFIG XDP_RX_PHY_CONFIG
	PHY reset and config. More...

#define	XDPRXSS_PHY_POWER_DOWN XDP_RX_PHY_POWER_DOWN
	PHY power down. More...

#define	XDPRXSS_MSA_HRES XDP_RX_MSA_HRES
	Number of active pixels per line (the horizontal resolution). More...

#define	XDPRXSS_MSA_VRES XDP_RX_MSA_VHEIGHT
	Number of active lines (the vertical resolution). More...

#define	XDPRXSS_NUM_STREAMS 4
	Maximum number of streams supported. More...

#define	XDPRXSS_MAX_NPORTS XDP_MAX_NPORTS
	Maximum number of RX ports. More...

#define	XDPRXSS_GUID_NBYTES XDP_GUID_NBYTES
	Number of bytes for GUID. More...

#define	XDPRXSS_TMRCTR_RST_VAL 100000000
	Timer Counter reset value. More...

#define	XDPRXSS_MCDP6000_IIC_SLAVE 0x14
	MCDP6000 slave device. More...

Typedefs
typedef void(*	XDpRxSs_Callback )(void *InstancePtr)
	Callback type which represents the handler for events. More...

Enumerations
enum	XDpRxSs_HdcpProtocol { XDPRXSS_HDCP_NONE, XDPRXSS_HDCP_14, XDPRXSS_HDCP_22, XDPRXSS_HDCP_BOTH }
	These constants specify the HDCP protection schemes. More...

enum	XDpRxSs_HandlerType { XDPRXSS_HANDLER_DP_VM_CHG_EVENT = 1, XDPRXSS_HANDLER_DP_PWR_CHG_EVENT, XDPRXSS_HANDLER_DP_NO_VID_EVENT, XDPRXSS_HANDLER_DP_VBLANK_EVENT, XDPRXSS_HANDLER_DP_TLOST_EVENT, XDPRXSS_HANDLER_DP_VID_EVENT, XDPRXSS_HANDLER_DP_INFO_PKT_EVENT, XDPRXSS_HANDLER_DP_EXT_PKT_EVENT, XDPRXSS_HANDLER_DP_TDONE_EVENT, XDPRXSS_HANDLER_DP_BW_CHG_EVENT, XDPRXSS_HANDLER_DP_DWN_REQ_EVENT, XDPRXSS_HANDLER_DP_DWN_REP_EVENT, XDPRXSS_HANDLER_DP_AUD_OVRFLW_EVENT, XDPRXSS_HANDLER_DP_PAYLOAD_ALLOC_EVENT, XDPRXSS_HANDLER_DP_ACT_RX_EVENT, XDPRXSS_HANDLER_DP_CRC_TEST_EVENT, XDPRXSS_HANDLER_UNPLUG_EVENT, XDPRXSS_HANDLER_LINKBW_EVENT, XDPRXSS_HANDLER_PLL_RESET_EVENT, XDPRXSS_DRV_HANDLER_DP_PWR_CHG_EVENT, XDPRXSS_DRV_HANDLER_DP_VID_EVENT, XDPRXSS_DRV_HANDLER_DP_NO_VID_EVENT, XDPRXSS_HANDLER_ACCESS_LANE_SET_EVENT, XDPRXSS_HANDLER_ACCESS_LINK_QUAL_EVENT, XDPRXSS_HANDLER_ACCESS_ERROR_COUNTER_EVENT, XDPRXSS_HANDLER_DP_VBLANK_STREAM_2_EVENT, XDPRXSS_HANDLER_DP_VBLANK_STREAM_3_EVENT, XDPRXSS_HANDLER_DP_VBLANK_STREAM_4_EVENT, XDPRXSS_HANDLER_DP_ADAPTIVESYNC_SDP_STREAM_1_EVENT, XDPRXSS_HANDLER_DP_ADAPTIVESYNC_SDP_STREAM_2_EVENT, XDPRXSS_HANDLER_DP_ADAPTIVESYNC_SDP_STREAM_3_EVENT, XDPRXSS_HANDLER_DP_ADAPTIVESYNC_SDP_STREAM_4_EVENT, XDPRXSS_HANDLER_DP_ADAPTIVESYNC_VBLANK_STREAM_1_EVENT, XDPRXSS_HANDLER_DP_ADAPTIVESYNC_VBLANK_STREAM_2_EVENT, XDPRXSS_HANDLER_DP_ADAPTIVESYNC_VBLANK_STREAM_3_EVENT, XDPRXSS_HANDLER_DP_ADAPTIVESYNC_VBLANK_STREAM_4_EVENT, XDPRXSS_HANDLER_DP_VM_CHG_STREAM_2_EVENT, XDPRXSS_HANDLER_DP_VM_CHG_STREAM_3_EVENT, XDPRXSS_HANDLER_DP_VM_CHG_STREAM_4_EVENT, XDPRXSS_HANDLER_DP_NO_VID_STREAM_2_EVENT, XDPRXSS_HANDLER_DP_NO_VID_STREAM_3_EVENT, XDPRXSS_HANDLER_DP_NO_VID_STREAM_4_EVENT, XDPRXSS_HANDLER_DP_VID_STREAM_2_EVENT, XDPRXSS_HANDLER_DP_VID_STREAM_3_EVENT, XDPRXSS_HANDLER_DP_VID_STREAM_4_EVENT, XDPRXSS_HANDLER_DP_INFO_PKT_STREAM_2_EVENT, XDPRXSS_HANDLER_DP_INFO_PKT_STREAM_3_EVENT, XDPRXSS_HANDLER_DP_INFO_PKT_STREAM_4_EVENT, XDPRXSS_HANDLER_DP_EXT_PKT_STREAM_2_EVENT, XDPRXSS_HANDLER_DP_EXT_PKT_STREAM_3_EVENT, XDPRXSS_HANDLER_DP_EXT_PKT_STREAM_4_EVENT }
	These constants specify different types of handler and used to differentiate interrupt requests from sub-cores. More...

Functions
u32	XDpRxSs_CfgInitialize (XDpRxSs InstancePtr, XDpRxSs_Config CfgPtr, UINTPTR EffectiveAddr)
	This function initializes the DisplayPort Receiver Subsystem core. More...

void	XDpRxSs_Reset (XDpRxSs *InstancePtr)
	This function resets the DisplayPort Receiver Subsystem including all sub-cores. More...

u32	XDpRxSs_Start (XDpRxSs *InstancePtr)
	This function starts the DisplayPort Receiver Subsystem including all sub-cores. More...

u32	XDpRxSs_SetLinkRate (XDpRxSs *InstancePtr, u8 LinkRate)
	This function sets the data rate to be used by the DisplayPort RX Subsystem core. More...

u32	XDpRxSs_SetLaneCount (XDpRxSs *InstancePtr, u8 LaneCount)
	This function sets the number of lanes to be used by DisplayPort RX Subsystem core. More...

u32	XDpRxSs_ExposePort (XDpRxSs *InstancePtr, u8 Port)
	This function allows the user to select number of ports to be exposed when replying to a LINK_ADDRESS sideband message and hides rest of the ports. More...

u32	XDpRxSs_CheckLinkStatus (XDpRxSs *InstancePtr)
	This function checks if the receiver's DisplayPort Configuration Data (DPCD) indicates that the receiver has achieved clock recovery, channel equalization, symbol lock, and interlane alignment for all lanes currently in use. More...

void	XDpRxSs_SetUserPixelWidth (XDpRxSs *InstancePtr, u8 UserPixelWidth)
	This function configures the number of pixels output through the user data interface. More...

u8	XDpRxss_GetBpc (XDpRxSs *InstancePtr, u8 Stream)
	This function extracts the bits per color from MISC0 or VSC SDP packet based on whether reception of colorimetry information through VSC SDP packets or through MISC registers of the stream. More...

u8	XDpRxss_GetColorComponent (XDpRxSs *InstancePtr, u8 Stream)
	This function extracts the color component format from MISC0 or VSC SDP packet based on whether reception of colorimetry information through VSC SDP packets or through MISC registers of the stream. More...

u8	XDpRxss_GetColorimetry (XDpRxSs *InstancePtr, u8 Stream)
	This function extracts the YCbCrColorimetry from MISC0 or VSC SDP packet based on whether reception of colorimetry information through VSC SDP packets or through MISC registers of the stream. More...

u8	XDpRxss_GetDynamicRange (XDpRxSs *InstancePtr, u8 Stream)
	This function extracts the dynamic range from MISC0 or VSC SDP packet based on whether reception of colorimetry information through VSC SDP packets or through MISC registers of the stream. More...

u32	XDpRxSs_HandleDownReq (XDpRxSs *InstancePtr)
	This function handles incoming sideband messages. More...

void	XDpRxSs_McDp6000_init (void *InstancePtr)
	This routine initializes the MCDP6000 part on the VFMC card used for DP 1.4. More...

void	XDpRxSs_SetAdaptiveSyncCaps (XDpRxSs *InstancePtr, u32 Enable)
	This function sets Adaptive-Sync capabilities to DisplayPort RX Subsystem. More...

void	XDpRxSs_MaskAdaptiveIntr (XDpRxSs *InstancePtr, u32 Mask)
	This function masks the Adaptive-Sync interrupts from DisplayPort RX Subsystem. More...

void	XDpRxSs_UnMaskAdaptiveIntr (XDpRxSs *InstancePtr, u32 Mask)
	This function unmasks Adaptive-Sync interrupt from DisplayPort RX Subsystem. More...

int	XDpRxSs_GetVblank (XDpRxSs *InstancePtr, u8 Stream)
	This function retrieves the current vblank value of the incoming video stream. More...

int	XDpRxSs_GetVtotal (XDpRxSs *InstancePtr, u8 Stream)
	This function retrieves the current VTotal value of the incoming video stream. More...

int	XDpRxSs_Get_Dec_Clk_Lock (XDpRxSs *InstancePtr)
	This function resets the Clock Wizard and waits for it to lock after the receiver decode clock has been reconfigured. More...

XDpRxSs_Config *	XDpRxSs_LookupConfig (UINTPTR BaseAddress)
	This function returns a reference to an XDpRxSs_Config structure based on the core id, DeviceId. More...

u32	XDpRxSs_GetDrvIndex (UINTPTR BaseAddress)
	This function returns the Index number of config table using BaseAddress. More...

void	XDpRxSs_ReportCoreInfo (XDpRxSs *InstancePtr)
	This function reports list of sub-cores included in DisplayPort RX Subsystem. More...

void	XDpRxSs_ReportLinkInfo (XDpRxSs *InstancePtr)
	This function prints the link status, selected resolution, link rate /lane count symbol error. More...

void	XDpRxSs_ReportMsaInfo (XDpRxSs *InstancePtr)
	This function prints the current main stream attributes from the DisplayPort RX core. More...

void	XDpRxSs_ReportHdcpInfo (XDpRxSs *InstancePtr)
	This function prints the debug display info of the HDCP interface. More...

u32	XDpRxSs_SelfTest (XDpRxSs *InstancePtr)
	This function performs self test on DisplayPort Receiver Subsystem sub-cores. More...

void	XDpRxSs_DpIntrHandler (void *InstancePtr)
	This function is the interrupt handler for the DisplayPort RX core operating in RX mode. More...

u32	XDpRxSs_SetCallBack (XDpRxSs InstancePtr, u32 HandlerType, void CallbackFunc, void *CallbackRef)
	This function installs an asynchronous callback function for the given HandlerType: More...

void	XDpRxSs_SetUserTimerHandler (XDpRxSs InstancePtr, XDpRxSs_TimerHandler CallbackFunc, void CallbackRef)
	This function installs a custom delay/sleep function to be used by the DisplayPort RX Subsystem. More...

void	XDpRxSs_DrvNoVideoHandler (void *InstancePtr)
	This function is the interrupt handler for No Video. More...

void	XDpRxSs_DrvVideoHandler (void *InstancePtr)
	This function is for the video interrupt handler. More...

void	XDpRxSs_DrvPowerChangeHandler (void *InstancePtr)
	This function is for the power change interrupt handler. More...

u32	XDpRxSs_MCDP6000_GetRegister (XDpRxSs *DpRxSsPtr, u8 I2CSlaveAddress, u16 RegisterAddress)
	This function reads a single 32b word from the MCDP6000 device. More...

int	XDpRxSs_MCDP6000_SetRegister (XDpRxSs *DpRxSsPtr, u8 I2CSlaveAddress, u16 RegisterAddress, u32 Value)
	This function writes a single 32b word to the MCDP6000 device. More...

int	XDpRxSs_MCDP6000_ModifyRegister (XDpRxSs *DpRxSsPtr, u8 I2CSlaveAddress, u16 RegisterAddress, u32 Value, u32 Mask)
	This function modifies a single 32b word from the MCDP6000 device. More...

int	XDpRxSs_MCDP6000_DpInit (XDpRxSs *DpRxSsPtr, u8 I2CSlaveAddress)
	This function initializes the MCDP6000 device with default values for DP use with the Video FMC. More...

int	XDpRxSs_MCDP6000_IbertInit (XDpRxSs *DpRxSsPtr, u8 I2CSlaveAddress)
	This function initializes the MCDP6000 device with default values for IBERT use with the Video FMC. More...

int	XDpRxSs_MCDP6000_ResetCrPath (XDpRxSs *DpRxSsPtr, u8 I2CSlaveAddress)
	This function requests a reset of the CR path of the MCDP6000 device. More...

int	XDpRxSs_MCDP6000_ResetDpPath (XDpRxSs *DpRxSsPtr, u8 I2CSlaveAddress)
	This function requests a reset of the DP path of the MCDP6000 device. More...

int	XDpRxSs_MCDP6000_EnablePrbs7_Tx (XDpRxSs *DpRxSsPtr, u8 I2CSlaveAddress)
	This function enables the PRBS7 output of the MCDP6000 device. More...

int	XDpRxSs_MCDP6000_EnablePrbs7_Rx (XDpRxSs *DpRxSsPtr, u8 I2CSlaveAddress)
	This function enables the PRBS7 counter mode in MC Rx path Used in DP PHY compliance mode. More...

int	XDpRxSs_MCDP6000_DisablePrbs7_Rx (XDpRxSs *DpRxSsPtr, u8 I2CSlaveAddress)
	This function Disables the PRBS7 counter mode in MC Rx path Used in DP PHY compliance mode. More...

int	XDpRxSs_MCDP6000_EnableCounter (XDpRxSs *DpRxSsPtr, u8 I2CSlaveAddress)
	This function enables symbol counter. More...

int	XDpRxSs_MCDP6000_ClearCounter (XDpRxSs *DpRxSsPtr, u8 I2CSlaveAddress)
	This function clears symbol counter. More...

int	XDpRxSs_MCDP6000_Read_ErrorCounters (XDpRxSs *DpRxSsPtr, u8 I2CSlaveAddress)
	This function reads error counters for all lanes. More...

void	XDpRxSs_MCDP6000_RegisterDump (XDpRxSs *DpRxSsPtr, u8 I2CSlaveAddress)
	This function displays a registerdump of the MCDP6000 device. More...

int	XDpRxSs_MCDP6000_TransparentMode (XDpRxSs *DpRxSsPtr, u8 I2CSlaveAddress)
	This function sets the transparent mode of the MCDP6000 device. More...

int	XDpRxSs_MCDP6000_BWchange (XDpRxSs *DpRxSsPtr, u8 I2CSlaveAddress)
	This function changes the bandwidth of the MCDP6000 device. More...

int	XDpRxSs_MCDP6000_AccessLaneSet (XDpRxSs *DpRxSsPtr, u8 I2CSlaveAddress)
	This function sets the access lane register of the MCDP6000 device. More...

Clock Wizard register offsets and default values
#define	XCLK_WIZ_SWRST_OFFSET 0x00000000
	Software reset offset. More...

#define	XCLK_WIZ_SWRST_VAL 0x0A
	Software reset value. More...

#define	XCLK_WIZ_STATUS_OFFSET 0x00000004
	Status register offset. More...

#define	XCLK_WIZ_ISR_OFFSET 0x0000000C
	Interrupt status register offset. More...

#define	XCLK_WIZ_IER_OFFSET 0x00000010
	Interrupt enable register offset. More...

#define	XCLK_WIZ_RECONFIG_OFFSET 0x00000014
	Reconfiguration register offset. More...

#define	XCLK_WIZ_RECONFIG_VAL 0x03
	Reconfiguration trigger value. More...

#define	XCLK_WIZ_REG1_OFFSET 0x00000330
	ClkOut0 register 1 offset. More...

#define	XCLK_WIZ_REG2_OFFSET 0x00000334
	ClkOut0 register 2 offset. More...

#define	XCLK_WIZ_REG3_OFFSET 0x00000338
	ClkOut0 register 3 offset. More...

#define	XCLK_WIZ_REG4_OFFSET 0x0000033C
	ClkOut0 register 4 offset. More...

#define	XCLK_WIZ_REG12_OFFSET 0x00000380
	Divider register offset. More...

#define	XCLK_WIZ_REG13_OFFSET 0x00000384
	Divider register 2 offset. More...

#define	XCLK_WIZ_REG11_OFFSET 0x00000378
	ClkOut0 register 11 offset. More...

#define	XCLK_WIZ_REG11_VAL 0x2E
	ClkOut0 register 11 default value. More...

#define	XCLK_WIZ_REG14_OFFSET 0x00000398
	Filter register offset. More...

#define	XCLK_WIZ_REG14_VAL 0xE80
	Filter register default value. More...

#define	XCLK_WIZ_REG15_OFFSET 0x0000039C
	Lock register 1 offset. More...

#define	XCLK_WIZ_REG15_VAL 0x4271
	Lock register 1 default value. More...

#define	XCLK_WIZ_REG16_OFFSET 0x000003A0
	Lock register 2 offset. More...

#define	XCLK_WIZ_REG16_VAL 0x43E9
	Lock register 2 default value. More...

#define	XCLK_WIZ_REG17_OFFSET 0x000003A8
	Lock register 3 offset. More...

#define	XCLK_WIZ_REG17_VAL 0x1C
	Lock register 3 default value. More...

#define	XCLK_WIZ_REG19_OFFSET 0x000003CC
	Power register offset. More...

#define	XCLK_WIZ_REG25_OFFSET 0x000003F0
	FBout register offset. More...

#define	XCLK_WIZ_REG26_OFFSET 0x000003FC
	FBout register 2 offset. More...

#define	XCLK_WIZ_REG26_VAL 0x01
	FBout register 2 default value. More...

CLKx5 Wizard per-link-rate configuration values
#define	XCLK_WIZ_REG2_810GBPS_CFG_VAL 0x0E0E
	8.1 Gbps configuration values More...

#define	XCLK_WIZ_REG3_810GBPS_CFG_VAL 0xBB00
	Reg3 config for 8.1 Gbps. More...

#define	XCLK_WIZ_REG4_810GBPS_CFG_VAL 0x0101
	Reg4 config for 8.1 Gbps. More...

#define	XCLK_WIZ_REG11_810GBPS_CFG_VAL 0x002E
	Reg11 config for 8.1 Gbps. More...

#define	XCLK_WIZ_REG15_810GBPS_CFG_VAL 0x420D
	Reg15 config for 8.1 Gbps. More...

#define	XCLK_WIZ_REG17_810GBPS_CFG_VAL 0x0002
	Reg17 config for 8.1 Gbps. More...

#define	XCLK_WIZ_PRIM_L_810GBPS_CFG_VAL 0xB98A
	Primary low config for 8.1 Gbps. More...

#define	XCLK_WIZ_PRIM_H_810GBPS_CFG_VAL 0x0007
	Primary high config for 8.1 Gbps. More...

#define	XCLK_WIZ_SEC_L_810GBPS_CFG_VAL 0xDCC5
	Secondary low config for 8.1 Gbps. More...

#define	XCLK_WIZ_SEC_H_810GBPS_CFG_VAL 0x0003
	Secondary high config for 8.1 Gbps. More...

#define	XCLK_WIZ_REG2_540GBPS_CFG_VAL 0x1616
	5.4 Gbps configuration values More...

#define	XCLK_WIZ_REG3_540GBPS_CFG_VAL 0xBB00
	Reg3 config for 5.4 Gbps. More...

#define	XCLK_WIZ_REG4_540GBPS_CFG_VAL 0x0202
	Reg4 config for 5.4 Gbps. More...

#define	XCLK_WIZ_REG11_540GBPS_CFG_VAL 0x002F
	Reg11 config for 5.4 Gbps. More...

#define	XCLK_WIZ_REG15_540GBPS_CFG_VAL 0x412C
	Reg15 config for 5.4 Gbps. More...

#define	XCLK_WIZ_REG17_540GBPS_CFG_VAL 0x000C
	Reg17 config for 5.4 Gbps. More...

#define	XCLK_WIZ_PRIM_L_540GBPS_CFG_VAL 0x265C
	Primary low config for 5.4 Gbps. More...

#define	XCLK_WIZ_PRIM_H_540GBPS_CFG_VAL 0x0005
	Primary high config for 5.4 Gbps. More...

#define	XCLK_WIZ_SEC_L_540GBPS_CFG_VAL 0x932E
	Secondary low config for 5.4 Gbps. More...

#define	XCLK_WIZ_SEC_H_540GBPS_CFG_VAL 0x0002
	Secondary high config for 5.4 Gbps. More...

#define	XCLK_WIZ_REG2_270GBPS_CFG_VAL 0x2C2C
	2.7 Gbps configuration values More...

#define	XCLK_WIZ_REG3_270GBPS_CFG_VAL 0x1B00
	Reg3 config for 2.7 Gbps. More...

#define	XCLK_WIZ_REG4_270GBPS_CFG_VAL 0x0505
	Reg4 config for 2.7 Gbps. More...

#define	XCLK_WIZ_REG11_270GBPS_CFG_VAL 0x002E
	Reg11 config for 2.7 Gbps. More...

#define	XCLK_WIZ_REG15_270GBPS_CFG_VAL 0x40FA
	Reg15 config for 2.7 Gbps. More...

#define	XCLK_WIZ_REG17_270GBPS_CFG_VAL 0x0004
	Reg17 config for 2.7 Gbps. More...

#define	XCLK_WIZ_PRIM_L_270GBPS_CFG_VAL 0x932E
	Primary low config for 2.7 Gbps. More...

#define	XCLK_WIZ_PRIM_H_270GBPS_CFG_VAL 0x0002
	Primary high config for 2.7 Gbps. More...

#define	XCLK_WIZ_SEC_L_270GBPS_CFG_VAL 0x86A0
	Secondary low config for 2.7 Gbps. More...

#define	XCLK_WIZ_SEC_H_270GBPS_CFG_VAL 0x0001
	Secondary high config for 2.7 Gbps. More...

#define	XCLK_WIZ_REG2_162GBPS_CFG_VAL 0x4A4A
	1.62 Gbps configuration values More...

#define	XCLK_WIZ_REG3_162GBPS_CFG_VAL 0xBA00
	Reg3 config for 1.62 Gbps. More...

#define	XCLK_WIZ_REG4_162GBPS_CFG_VAL 0x0909
	Reg4 config for 1.62 Gbps. More...

#define	XCLK_WIZ_REG11_162GBPS_CFG_VAL 0x002C
	Reg11 config for 1.62 Gbps. More...

#define	XCLK_WIZ_REG15_162GBPS_CFG_VAL 0x40FA
	Reg15 config for 1.62 Gbps. More...

#define	XCLK_WIZ_REG17_162GBPS_CFG_VAL 0x0008
	Reg17 config for 1.62 Gbps. More...

#define	XCLK_WIZ_PRIM_L_162GBPS_CFG_VAL 0x8B82
	Primary low config for 1.62 Gbps. More...

#define	XCLK_WIZ_PRIM_H_162GBPS_CFG_VAL 0x0001
	Primary high config for 1.62 Gbps. More...

#define	XCLK_WIZ_SEC_L_162GBPS_CFG_VAL 0x86A0
	Secondary low config for 1.62 Gbps. More...

#define	XCLK_WIZ_SEC_H_162GBPS_CFG_VAL 0x0001
	Secondary high config for 1.62 Gbps. More...

Clock Wizard control bit masks and shift values
#define	XCLK_WIZ_LOCK 1
	Clock lock status bit. More...

#define	XCLK_WIZ_REG3_PREDIV2 (1 << 11)
	ClkOut0 reg3 pre-divide by 2. More...

#define	XCLK_WIZ_REG3_USED (1 << 12)
	ClkOut0 reg3 used bit. More...

#define	XCLK_WIZ_REG3_MX (1 << 9)
	ClkOut0 reg3 MX bit. More...

#define	XCLK_WIZ_REG1_PREDIV2 (1 << 12)
	FBout reg1 pre-divide by 2. More...

#define	XCLK_WIZ_REG1_EN (1 << 9)
	FBout enable bit. More...

#define	XCLK_WIZ_REG1_MX (1 << 10)
	FBout MX bit. More...

#define	XCLK_WIZ_RECONFIG_LOAD 1
	Reconfiguration load trigger. More...

#define	XCLK_WIZ_RECONFIG_SADDR 2
	Reconfiguration start address. More...

#define	XCLK_WIZ_REG1_EDGE_MASK (1 << 8)
	FBout reg1 edge mask. More...

#define	XCLK_WIZ_CLKOUT0_PREDIV2_SHIFT 11
	ClkOut0 pre-divide by 2 shift. More...

#define	XCLK_WIZ_CLKOUT0_MX_SHIFT 9
	ClkOut0 MX shift. More...

#define	XCLK_WIZ_CLKOUT0_P5EN_SHIFT 13
	ClkOut0 phase5 enable shift. More...

#define	XCLK_WIZ_CLKOUT0_P5FEDGE_SHIFT 15
	ClkOut0 phase5 falling edge shift. More...

#define	XCLK_WIZ_REG12_EDGE_SHIFT 10
	Divider edge shift. More...

MMCM multiplier and divider values
#define	M_VAL_405 28
	MMCM multiplier for 405 MHz (8.1 Gbps link rate) More...

#define	M_VAL_270 44
	MMCM multiplier for 270 MHz (5.4 Gbps link rate) More...

#define	M_VAL_135 88
	MMCM multiplier for 135 MHz (2.7 Gbps link rate) More...

#define	M_VAL_81 148
	MMCM multiplier for 81 MHz (1.62 Gbps link rate) More...

#define	D_VAL_ALL 5
	MMCM divider value for all link rates. More...

u8	GenEdid [128]
	A generic EDID (Extended Display Identification Data) structure. More...

u8	GenDpcd []
	A generic DPCD (DisplayPort Configuration Data) structure. More...

XDpRxSs_SubCores	DpRxSsSubCores [XPAR_XDPRXSS_NUM_INSTANCES]
	DisplayPort RX subcores instance array. More...

Register access macro definition
#define	XDpRxSs_In32 Xil_In32
	Input Operations. More...

#define	XDpRxSs_Out32 Xil_Out32
	Output Operations. More...

#define	XDpRxSs_ReadReg(BaseAddress, RegOffset) XDpRxSs_In32((BaseAddress) + ((u32)RegOffset))
	This macro reads a value from a DisplayPort Receiver Subsystem register. More...

#define	XDpRxSs_WriteReg(BaseAddress, RegOffset, Data) XDpRxSs_Out32((BaseAddress) + ((u32)RegOffset), (u32)(Data))
	This macro writes a value to a DisplayPort Receiver Subsystem register. More...

Macro Definition Documentation

#define D_VAL_ALL 5

MMCM divider value for all link rates.

#define EDID_IIC_ADDRESS 0x50

EDID IIC slave address.

#define M_VAL_135 88

MMCM multiplier for 135 MHz (2.7 Gbps link rate)

#define M_VAL_270 44

MMCM multiplier for 270 MHz (5.4 Gbps link rate)

#define M_VAL_405 28

MMCM multiplier for 405 MHz (8.1 Gbps link rate)

#define M_VAL_81 148

MMCM multiplier for 81 MHz (1.62 Gbps link rate)

#define XCLK_WIZ_CLKOUT0_MX_SHIFT 9

ClkOut0 MX shift.

#define XCLK_WIZ_CLKOUT0_P5EN_SHIFT 13

ClkOut0 phase5 enable shift.

#define XCLK_WIZ_CLKOUT0_P5FEDGE_SHIFT 15

ClkOut0 phase5 falling edge shift.

#define XCLK_WIZ_CLKOUT0_PREDIV2_SHIFT 11

ClkOut0 pre-divide by 2 shift.

#define XCLK_WIZ_IER_OFFSET 0x00000010

Interrupt enable register offset.

#define XCLK_WIZ_ISR_OFFSET 0x0000000C

Interrupt status register offset.

#define XCLK_WIZ_LOCK 1

Clock lock status bit.

#define XCLK_WIZ_PRIM_H_162GBPS_CFG_VAL 0x0001

Primary high config for 1.62 Gbps.

#define XCLK_WIZ_PRIM_H_270GBPS_CFG_VAL 0x0002

Primary high config for 2.7 Gbps.

#define XCLK_WIZ_PRIM_H_540GBPS_CFG_VAL 0x0005

Primary high config for 5.4 Gbps.

#define XCLK_WIZ_PRIM_H_810GBPS_CFG_VAL 0x0007

Primary high config for 8.1 Gbps.

#define XCLK_WIZ_PRIM_H_OFFSET 0x000003B4

Clock Wizard primary high offset.

#define XCLK_WIZ_PRIM_L_162GBPS_CFG_VAL 0x8B82

Primary low config for 1.62 Gbps.

#define XCLK_WIZ_PRIM_L_270GBPS_CFG_VAL 0x932E

Primary low config for 2.7 Gbps.

#define XCLK_WIZ_PRIM_L_540GBPS_CFG_VAL 0x265C

Primary low config for 5.4 Gbps.

#define XCLK_WIZ_PRIM_L_810GBPS_CFG_VAL 0xB98A

Primary low config for 8.1 Gbps.

#define XCLK_WIZ_PRIM_L_OFFSET 0x000003B0

Clock Wizard primary low offset.

#define XCLK_WIZ_RECONFIG_LOAD 1

Reconfiguration load trigger.

#define XCLK_WIZ_RECONFIG_OFFSET 0x00000014

Reconfiguration register offset.

#define XCLK_WIZ_RECONFIG_SADDR 2

Reconfiguration start address.

#define XCLK_WIZ_RECONFIG_VAL 0x03

Reconfiguration trigger value.

#define XCLK_WIZ_REG11_162GBPS_CFG_VAL 0x002C

Reg11 config for 1.62 Gbps.

#define XCLK_WIZ_REG11_270GBPS_CFG_VAL 0x002E

Reg11 config for 2.7 Gbps.

#define XCLK_WIZ_REG11_540GBPS_CFG_VAL 0x002F

Reg11 config for 5.4 Gbps.

#define XCLK_WIZ_REG11_810GBPS_CFG_VAL 0x002E

Reg11 config for 8.1 Gbps.

#define XCLK_WIZ_REG11_OFFSET 0x00000378

ClkOut0 register 11 offset.

#define XCLK_WIZ_REG11_VAL 0x2E

ClkOut0 register 11 default value.

#define XCLK_WIZ_REG12_EDGE_SHIFT 10

Divider edge shift.

#define XCLK_WIZ_REG12_OFFSET 0x00000380

Divider register offset.

#define XCLK_WIZ_REG13_OFFSET 0x00000384

Divider register 2 offset.

#define XCLK_WIZ_REG14_OFFSET 0x00000398

Filter register offset.

#define XCLK_WIZ_REG14_VAL 0xE80

Filter register default value.

#define XCLK_WIZ_REG15_162GBPS_CFG_VAL 0x40FA

Reg15 config for 1.62 Gbps.

#define XCLK_WIZ_REG15_270GBPS_CFG_VAL 0x40FA

Reg15 config for 2.7 Gbps.

#define XCLK_WIZ_REG15_540GBPS_CFG_VAL 0x412C

Reg15 config for 5.4 Gbps.

#define XCLK_WIZ_REG15_810GBPS_CFG_VAL 0x420D

Reg15 config for 8.1 Gbps.

#define XCLK_WIZ_REG15_OFFSET 0x0000039C

Lock register 1 offset.

#define XCLK_WIZ_REG15_VAL 0x4271

Lock register 1 default value.

#define XCLK_WIZ_REG16_OFFSET 0x000003A0

Lock register 2 offset.

#define XCLK_WIZ_REG16_VAL 0x43E9

Lock register 2 default value.

#define XCLK_WIZ_REG17_162GBPS_CFG_VAL 0x0008

Reg17 config for 1.62 Gbps.

#define XCLK_WIZ_REG17_270GBPS_CFG_VAL 0x0004

Reg17 config for 2.7 Gbps.

#define XCLK_WIZ_REG17_540GBPS_CFG_VAL 0x000C

Reg17 config for 5.4 Gbps.

#define XCLK_WIZ_REG17_810GBPS_CFG_VAL 0x0002

Reg17 config for 8.1 Gbps.

#define XCLK_WIZ_REG17_OFFSET 0x000003A8

Lock register 3 offset.

#define XCLK_WIZ_REG17_VAL 0x1C

Lock register 3 default value.

#define XCLK_WIZ_REG19_OFFSET 0x000003CC

Power register offset.

#define XCLK_WIZ_REG1_EDGE_MASK (1 << 8)

FBout reg1 edge mask.

#define XCLK_WIZ_REG1_EN (1 << 9)

FBout enable bit.

#define XCLK_WIZ_REG1_MX (1 << 10)

FBout MX bit.

#define XCLK_WIZ_REG1_OFFSET 0x00000330

ClkOut0 register 1 offset.

#define XCLK_WIZ_REG1_PREDIV2 (1 << 12)

FBout reg1 pre-divide by 2.

#define XCLK_WIZ_REG25_OFFSET 0x000003F0

FBout register offset.

#define XCLK_WIZ_REG26_OFFSET 0x000003FC

FBout register 2 offset.

#define XCLK_WIZ_REG26_VAL 0x01

FBout register 2 default value.

#define XCLK_WIZ_REG2_162GBPS_CFG_VAL 0x4A4A

1.62 Gbps configuration values

#define XCLK_WIZ_REG2_270GBPS_CFG_VAL 0x2C2C

2.7 Gbps configuration values

#define XCLK_WIZ_REG2_540GBPS_CFG_VAL 0x1616

5.4 Gbps configuration values

#define XCLK_WIZ_REG2_810GBPS_CFG_VAL 0x0E0E

8.1 Gbps configuration values

#define XCLK_WIZ_REG2_OFFSET 0x00000334

ClkOut0 register 2 offset.

#define XCLK_WIZ_REG3_162GBPS_CFG_VAL 0xBA00

Reg3 config for 1.62 Gbps.

#define XCLK_WIZ_REG3_270GBPS_CFG_VAL 0x1B00

Reg3 config for 2.7 Gbps.

#define XCLK_WIZ_REG3_540GBPS_CFG_VAL 0xBB00

Reg3 config for 5.4 Gbps.

#define XCLK_WIZ_REG3_810GBPS_CFG_VAL 0xBB00

Reg3 config for 8.1 Gbps.

#define XCLK_WIZ_REG3_MX (1 << 9)

ClkOut0 reg3 MX bit.

#define XCLK_WIZ_REG3_OFFSET 0x00000338

ClkOut0 register 3 offset.

#define XCLK_WIZ_REG3_PREDIV2 (1 << 11)

ClkOut0 reg3 pre-divide by 2.

#define XCLK_WIZ_REG3_USED (1 << 12)

ClkOut0 reg3 used bit.

#define XCLK_WIZ_REG4_162GBPS_CFG_VAL 0x0909

Reg4 config for 1.62 Gbps.

#define XCLK_WIZ_REG4_270GBPS_CFG_VAL 0x0505

Reg4 config for 2.7 Gbps.

#define XCLK_WIZ_REG4_540GBPS_CFG_VAL 0x0202

Reg4 config for 5.4 Gbps.

#define XCLK_WIZ_REG4_810GBPS_CFG_VAL 0x0101

Reg4 config for 8.1 Gbps.

#define XCLK_WIZ_REG4_OFFSET 0x0000033C

ClkOut0 register 4 offset.

#define XCLK_WIZ_SEC_H_162GBPS_CFG_VAL 0x0001

Secondary high config for 1.62 Gbps.

#define XCLK_WIZ_SEC_H_270GBPS_CFG_VAL 0x0001

Secondary high config for 2.7 Gbps.

#define XCLK_WIZ_SEC_H_540GBPS_CFG_VAL 0x0002

Secondary high config for 5.4 Gbps.

#define XCLK_WIZ_SEC_H_810GBPS_CFG_VAL 0x0003

Secondary high config for 8.1 Gbps.

#define XCLK_WIZ_SEC_H_OFFSET 0x000003BC

Clock Wizard secondary high offset.

#define XCLK_WIZ_SEC_L_162GBPS_CFG_VAL 0x86A0

Secondary low config for 1.62 Gbps.

#define XCLK_WIZ_SEC_L_270GBPS_CFG_VAL 0x86A0

Secondary low config for 2.7 Gbps.

#define XCLK_WIZ_SEC_L_540GBPS_CFG_VAL 0x932E

Secondary low config for 5.4 Gbps.

#define XCLK_WIZ_SEC_L_810GBPS_CFG_VAL 0xDCC5

Secondary low config for 8.1 Gbps.

#define XCLK_WIZ_SEC_L_OFFSET 0x000003B8

Clock Wizard secondary low offset.

#define XCLK_WIZ_STATUS_OFFSET 0x00000004

Status register offset.

Referenced by XDpRxSs_Get_Dec_Clk_Lock().

#define XCLK_WIZ_STATUS_RETRY 10000

Max retries for clock lock status.

Referenced by XDpRxSs_Get_Dec_Clk_Lock().

#define XCLK_WIZ_STATUS_WAIT 100

Wait time in microseconds between retries.

Referenced by XDpRxSs_Get_Dec_Clk_Lock().

#define XCLK_WIZ_SWRST_OFFSET 0x00000000

Software reset offset.

Referenced by XDpRxSs_Get_Dec_Clk_Lock().

#define XCLK_WIZ_SWRST_VAL 0x0A

Software reset value.

Referenced by XDpRxSs_Get_Dec_Clk_Lock().

#define XDpRxSs_AudioDisable ( InstancePtr ) XDp_RxAudioDis((InstancePtr)->DpPtr)

This function macro disables audio stream packets on the main link.

Parameters

InstancePtr is a pointer to the XDpRxSs core instance.

Returns: None.

Note: C-style signature: void XDpRxSs_AudioDisable(XDpRxSs *InstancePtr)

Referenced by DpRxSs_Main(), DpRxSs_TrainingLostHandler(), and DpRxSs_UnplugHandler().

#define XDpRxSs_AudioEnable ( InstancePtr ) XDp_RxAudioEn((InstancePtr)->DpPtr)

This function macro enables audio stream packets on the main link.

Parameters

InstancePtr is a pointer to the XDpRxSs core instance.

Returns: None.

Note: C-style signature: void XDpRxSs_AudioEnable(XDpRxSs *InstancePtr)

Referenced by DpRxSs_Main().

#define XDpRxSs_AudioReset ( InstancePtr ) XDp_RxAudioReset((InstancePtr)->DpPtr)

This function macro resets the reception of audio stream packets on the main link.

Parameters

InstancePtr is a pointer to the XDpRxSs core instance.

Note: C-style signature: void XDpRxSs_AudioReset(XDpRxSs *InstancePtr)

#define XDpRxSs_DtgDisable ( InstancePtr ) XDp_RxDtgDis((InstancePtr)->DpPtr)

This function macro disables the display timing generator (DTG).

Parameters

InstancePtr is a pointer to the XDpRxSs core instance.

Returns: None.

Note: C-style signature: void XDpRxSs_DtgDisable(XDpRxSs *InstancePtr)

#define XDpRxSs_DtgEnable ( InstancePtr ) XDp_RxDtgEn((InstancePtr)->DpPtr)

This function macro enables the display timing generator (DTG).

Parameters

InstancePtr is a pointer to the XDpRxSs core instance.

Returns: None.

Note: C-style signature: void XDpRxSs_DtgEnable(XDpRxSs *InstancePtr)

#define XDPRXSS_GUID_NBYTES XDP_GUID_NBYTES

Number of bytes for GUID.

#define XDPRXSS_H_

Prevent circular inclusions by using protection macros.

#define XDPRXSS_HW_H_

Prevent circular inclusions by using protection macros.

#define XDpRxSs_In32 Xil_In32

Input Operations.

#define XDPRXSS_LANE_COUNT_SET_1 XDP_RX_OVER_LANE_COUNT_SET_1

Lane count of 1.

Referenced by XDpRxSs_SetLaneCount().

#define XDPRXSS_LANE_COUNT_SET_2 XDP_RX_OVER_LANE_COUNT_SET_2

Lane count of 2.

Referenced by XDpRxSs_SetLaneCount().

#define XDPRXSS_LANE_COUNT_SET_4 XDP_RX_OVER_LANE_COUNT_SET_4

Lane count of 4.

Referenced by XDpRxSs_SetLaneCount().

#define XDPRXSS_LINK_BW_SET_162GBPS XDP_RX_OVER_LINK_BW_SET_162GBPS

1.62 Gbps link rate.

Referenced by XDpRxSs_SetLinkRate().

#define XDPRXSS_LINK_BW_SET_270GBPS XDP_RX_OVER_LINK_BW_SET_270GBPS

2.70 Gbps link rate.

Referenced by XDpRxSs_SetLinkRate().

#define XDPRXSS_LINK_BW_SET_540GBPS XDP_RX_OVER_LINK_BW_SET_540GBPS

5.40 Gbps link rate.

Referenced by XDpRxSs_SetLinkRate().

#define XDPRXSS_LINK_BW_SET_810GBPS XDP_RX_OVER_LINK_BW_SET_810GBPS

8.10 Gbps link rate.

Referenced by XDpRxSs_SetLinkRate().

#define XDPRXSS_MAX_NPORTS XDP_MAX_NPORTS

Maximum number of RX ports.

#define XDPRXSS_MCDP6000_IIC_SLAVE 0x14

MCDP6000 slave device.

Referenced by XDpRxSs_McDp6000_init().

#define XDPRXSS_MSA_HRES XDP_RX_MSA_HRES

Number of active pixels per line (the horizontal resolution).

Referenced by DpRxSs_DetectResolution().

#define XDPRXSS_MSA_VRES XDP_RX_MSA_VHEIGHT

Number of active lines (the vertical resolution).

Referenced by DpRxSs_DetectResolution().

#define XDpRxSs_Mst_AudioDisable ( InstancePtr ) XDp_RxAudioDis((InstancePtr)->DpPtr)

This function macro disables audio on a given stream on the main link.

Parameters

InstancePtr is a pointer to the XDpRxSs core instance.

Returns: None.

Note: C-style signature: void XDpRxSs_Mst_AudioDisable(XDpRxSs *InstancePtr)

#define XDpRxSs_Mst_AudioEnable	(	InstancePtr,
		StreamId
	)	XDp_Rx_Mst_AudioEn((InstancePtr)->DpPtr, StreamId)

This function macro enables MST audio on a given stream on the main link.

Parameters

InstancePtr	is a pointer to the XDpRxSs core instance.
StreamId	to be enabled audio

Returns: None.

Note: C-style signature: void XDpRxSs_Mst_AudioEnable(XDpRxSs *InstancePtr, u8 StreamId)

#define XDPRXSS_NUM_STREAMS 4

Maximum number of streams supported.

#define XDpRxSs_Out32 Xil_Out32

Output Operations.

#define XDPRXSS_PHY_POWER_DOWN XDP_RX_PHY_POWER_DOWN

PHY power down.

#define XDpRxSs_ReadReg	(	BaseAddress,
		RegOffset
	)	XDpRxSs_In32((BaseAddress) + ((u32)RegOffset))

This macro reads a value from a DisplayPort Receiver Subsystem register.

A 32 bit read is performed. If the component is implemented in a smaller width, only the least significant data is read from the register. The most significant data will be read as 0.

Parameters

BaseAddress	is the base address of the XDpRxSs core instance.
RegOffset	is the register offset of the register (defined at the top of this file).

Returns: The 32-bit value of the register.

Note: C-style signature: u32 XDpRxSs_ReadReg(UINTPTR BaseAddress, u32 RegOffset)

Referenced by DpRxSs_DetectResolution(), XDpRxSs_Get_Dec_Clk_Lock(), XDpRxSs_GetVblank(), XDpRxSs_GetVtotal(), XDpRxSs_MaskAdaptiveIntr(), XDpRxSs_ReportLinkInfo(), XDpRxSs_SetAdaptiveSyncCaps(), and XDpRxSs_UnMaskAdaptiveIntr().

#define XDPRXSS_RX_PHY_CONFIG XDP_RX_PHY_CONFIG

PHY reset and config.

#define XDpRxSs_TimerHandler XDp_TimerHandler

Callback type which represents a custom timer wait handler.

#define XDPRXSS_TMRCTR_RST_VAL 100000000

Timer Counter reset value.

Referenced by XDpRxSs_CfgInitialize().

#define XDpRxSs_WaitUs	(	InstancePtr,
		MicroSeconds
	)	XDp_WaitUs((InstancePtr)->DpPtr, MicroSeconds)

This function macro is the delay/sleep function for the XDpRxSs driver.

Parameters

InstancePtr	is a pointer to the XDpRxSs core instance.
MicroSeconds	is the number of microseconds to delay/sleep for.

Returns: None.

Note: C-style signature: void XDpRxSs_WaitUs(XDpRxSs *InstancePtr)

Referenced by DpRxSs_DetectResolution().

#define XDpRxSs_WriteReg	(	BaseAddress,
		RegOffset,
		Data
	)	XDpRxSs_Out32((BaseAddress) + ((u32)RegOffset), (u32)(Data))

This macro writes a value to a DisplayPort Receiver Subsystem register.

A 32 bit write is performed. If the component is implemented in a smaller width, only the least significant data is written.

Parameters

BaseAddress	is the base address of the XDpRxSs core instance.
RegOffset	is the register offset of the register (defined at the top of this file) to be written.
Data	is the 32-bit value to write into the register.

Returns: None.

Note: C-style signature: void XDpRxSs_WriteReg(UINTPTR BaseAddress, u32 RegOffset, u32 Data)

Referenced by XDpRxSs_Get_Dec_Clk_Lock(), XDpRxSs_MaskAdaptiveIntr(), XDpRxSs_Reset(), XDpRxSs_SetAdaptiveSyncCaps(), and XDpRxSs_UnMaskAdaptiveIntr().

Typedef Documentation

typedef void(* XDpRxSs_Callback)(void *InstancePtr)

Callback type which represents the handler for events.

Parameters

InstancePtr is a pointer to the XDpRxSs instance.

Note: None.

Enumeration Type Documentation

enum XDpRxSs_HandlerType

These constants specify different types of handler and used to differentiate interrupt requests from sub-cores.

Enumerator
XDPRXSS_HANDLER_DP_VM_CHG_EVENT	Video mode change event interrupt type for DisplayPort core.
XDPRXSS_HANDLER_DP_PWR_CHG_EVENT	Power state change interrupt type for DisplayPort core.
XDPRXSS_HANDLER_DP_NO_VID_EVENT	No video event interrupt type for DisplayPort core.
XDPRXSS_HANDLER_DP_VBLANK_EVENT	Vertical blanking event interrupt type for DisplayPort core.
XDPRXSS_HANDLER_DP_TLOST_EVENT	Training lost event interrupt type for DisplayPort core.
XDPRXSS_HANDLER_DP_VID_EVENT	Valid video event interrupt type for DisplayPort core.
XDPRXSS_HANDLER_DP_INFO_PKT_EVENT	Info packet event interrupt type for DisplayPort core.
XDPRXSS_HANDLER_DP_EXT_PKT_EVENT	Extension packet event interrupt type for DisplayPort core.
XDPRXSS_HANDLER_DP_TDONE_EVENT	Training done event interrupt type for DisplayPort core.
XDPRXSS_HANDLER_DP_BW_CHG_EVENT	Bandwidth change event interrupt type for DisplayPort core.
XDPRXSS_HANDLER_DP_DWN_REQ_EVENT	Down request event interrupt type for DisplayPort core.
XDPRXSS_HANDLER_DP_DWN_REP_EVENT	Down reply event interrupt type for DisplayPort core.
XDPRXSS_HANDLER_DP_AUD_OVRFLW_EVENT	Audio packet overflow event interrupt type for DisplayPort core.
XDPRXSS_HANDLER_DP_PAYLOAD_ALLOC_EVENT	Payload allocation event interrupt type for DisplayPort core.
XDPRXSS_HANDLER_DP_ACT_RX_EVENT	ACT sequence received event interrupt type for DisplayPort core.
XDPRXSS_HANDLER_DP_CRC_TEST_EVENT	CRC test start event interrupt type for DisplayPort core.
XDPRXSS_HANDLER_UNPLUG_EVENT	Unplug event type for DisplayPort RX Subsystem.
XDPRXSS_HANDLER_LINKBW_EVENT	Link BW event type for DisplayPort RX Subsystem.
XDPRXSS_HANDLER_PLL_RESET_EVENT	PLL reset event type for DisplayPort RX Subsystem.
XDPRXSS_DRV_HANDLER_DP_PWR_CHG_EVENT	Drv power state change interrupt type for DisplayPort core.
XDPRXSS_DRV_HANDLER_DP_VID_EVENT	Drv Valid video event interrupt type for DisplayPort core.
XDPRXSS_DRV_HANDLER_DP_NO_VID_EVENT	Drv No video event interrupt type for DisplayPort core.
XDPRXSS_HANDLER_ACCESS_LANE_SET_EVENT	Drv Access lane set interrupt type for DisplayPort core.
XDPRXSS_HANDLER_ACCESS_LINK_QUAL_EVENT	Drv Access link qual interrupt type for DisplayPort core.
XDPRXSS_HANDLER_ACCESS_ERROR_COUNTER_EVENT	Drv Access error counter interrupt type for DisplayPort core.
XDPRXSS_HANDLER_DP_VBLANK_STREAM_2_EVENT	Vertical blanking event for stream 2 interrupt type for DisplayPort core.
XDPRXSS_HANDLER_DP_VBLANK_STREAM_3_EVENT	Vertical blanking event for stream 3 interrupt type for DisplayPort core.
XDPRXSS_HANDLER_DP_VBLANK_STREAM_4_EVENT	Vertical blanking event for stream 4 interrupt type for DisplayPort core.
XDPRXSS_HANDLER_DP_ADAPTIVESYNC_SDP_STREAM_1_EVENT	Adaptive sync SDP packet event for stream 1 DisplayPort core.
XDPRXSS_HANDLER_DP_ADAPTIVESYNC_SDP_STREAM_2_EVENT	Adaptive sync SDP packet event for stream 2 DisplayPort core.
XDPRXSS_HANDLER_DP_ADAPTIVESYNC_SDP_STREAM_3_EVENT	Adaptive sync SDP packet event for stream 3 DisplayPort core.
XDPRXSS_HANDLER_DP_ADAPTIVESYNC_SDP_STREAM_4_EVENT	Adaptive sync SDP packet event for stream 4 DisplayPort core.
XDPRXSS_HANDLER_DP_ADAPTIVESYNC_VBLANK_STREAM_1_EVENT	Adaptive sync vblank event for stream 1 DisplayPort core.
XDPRXSS_HANDLER_DP_ADAPTIVESYNC_VBLANK_STREAM_2_EVENT	Adaptive sync vblank event for stream 2 DisplayPort core.
XDPRXSS_HANDLER_DP_ADAPTIVESYNC_VBLANK_STREAM_3_EVENT	Adaptive sync vblank event for stream 3 DisplayPort core.
XDPRXSS_HANDLER_DP_ADAPTIVESYNC_VBLANK_STREAM_4_EVENT	Adaptive sync vblank event for stream 4 DisplayPort core.
XDPRXSS_HANDLER_DP_VM_CHG_STREAM_2_EVENT	Video mode change event interrupt type for stream 2 DisplayPort core.
XDPRXSS_HANDLER_DP_VM_CHG_STREAM_3_EVENT	Video mode change event interrupt type for stream 3 DisplayPort core.
XDPRXSS_HANDLER_DP_VM_CHG_STREAM_4_EVENT	Video mode change event interrupt type for stream 4 DisplayPort core.
XDPRXSS_HANDLER_DP_NO_VID_STREAM_2_EVENT	No video event interrupt type for stream 2 DisplayPort core.
XDPRXSS_HANDLER_DP_NO_VID_STREAM_3_EVENT	No video event interrupt type for stream 3 DisplayPort core.
XDPRXSS_HANDLER_DP_NO_VID_STREAM_4_EVENT	No video event interrupt type for stream 4 DisplayPort core.
XDPRXSS_HANDLER_DP_VID_STREAM_2_EVENT	Valid video event interrupt type for stream 2 DisplayPort core.
XDPRXSS_HANDLER_DP_VID_STREAM_3_EVENT	Valid video event interrupt type for stream 3 DisplayPort core.
XDPRXSS_HANDLER_DP_VID_STREAM_4_EVENT	Valid video event interrupt type for stream 4 DisplayPort core.
XDPRXSS_HANDLER_DP_INFO_PKT_STREAM_2_EVENT	Info packet event interrupt type for stream 2 DisplayPort core.
XDPRXSS_HANDLER_DP_INFO_PKT_STREAM_3_EVENT	Info packet event interrupt type for stream 3 DisplayPort core.
XDPRXSS_HANDLER_DP_INFO_PKT_STREAM_4_EVENT	Info packet event interrupt type for stream 4 DisplayPort core.
XDPRXSS_HANDLER_DP_EXT_PKT_STREAM_2_EVENT	Extension packet event interrupt type for stream 2 DisplayPort core.
XDPRXSS_HANDLER_DP_EXT_PKT_STREAM_3_EVENT	Extension packet event interrupt type for stream 3 DisplayPort core.
XDPRXSS_HANDLER_DP_EXT_PKT_STREAM_4_EVENT	Extension packet event interrupt type for stream 4 DisplayPort core.

enum XDpRxSs_HdcpProtocol

These constants specify the HDCP protection schemes.

Enumerator
XDPRXSS_HDCP_NONE	No content protection.
XDPRXSS_HDCP_14	HDCP 1.4.
XDPRXSS_HDCP_22	HDCP 2.2.
XDPRXSS_HDCP_BOTH	Both HDCP 1.4 and 2.2.

Function Documentation

u32 XDpRxSs_CfgInitialize	(	XDpRxSs *	InstancePtr,
		XDpRxSs_Config *	CfgPtr,
		UINTPTR	EffectiveAddr
	)

This function initializes the DisplayPort Receiver Subsystem core.

This function must be called prior to using the core. Initialization of the core includes setting up the instance data and ensuring the hardware is in a quiescent state.

Parameters

InstancePtr	is a pointer to the XDpRxSs core instance.
CfgPtr	points to the configuration structure associated with the DisplayPort RX Subsystem core.
EffectiveAddr	is the base address of the device. If address translation is being used, then this parameter must reflect the virtual base address. Otherwise, the physical address should be used.

Returns

XST_DEVICE_NOT_FOUND if sub-core not found.
XST_FAILURE if sub-core initialization failed.
XST_SUCCESS if XDpRxSs_CfgInitialize successful.

Note: None.

References XDpRxSs_Config::BaseAddress, XDpRxSs_UsrOpt::Bpc, XDpRxSs_Config::ClkWizSubCore, XDpRxSs::Config, XDpRxSs_DpSubCore::DpConfig, XDpRxSs::DpPtr, XDpRxSs_Config::DpSubCore, XDpRxSs_Hdcp1xSubCore::Hdcp1xConfig, XDpRxSs_Config::Hdcp1xSubCore, XDpRxSs_Config::Hdcp22Enable, XDpRxSs_Config::HdcpEnable, XDpRxSs_Config::IicSubCore, XDpRxSs_Config::IncludeClkWiz, XDpRxSs::IsReady, XDpRxSs_UsrOpt::LaneCount, XDpRxSs_UsrOpt::LinkRate, XDpRxSs_Config::MaxBpc, XDpRxSs_Config::MaxLaneCount, XDpRxSs_UsrOpt::MstSupport, XDpRxSs_Config::MstSupport, XDpRxSs_Config::NumMstStreams, XDpRxSs_UsrOpt::NumOfStreams, XDpRxSs_Config::TmrCtrSubCore, XDpRxSs::UsrOpt, XDPRXSS_DRV_HANDLER_DP_NO_VID_EVENT, XDPRXSS_DRV_HANDLER_DP_PWR_CHG_EVENT, XDPRXSS_DRV_HANDLER_DP_VID_EVENT, XDpRxSs_DrvNoVideoHandler(), XDpRxSs_DrvPowerChangeHandler(), XDpRxSs_DrvVideoHandler(), XDPRXSS_HDCP_14, XDPRXSS_HDCP_22, XDpRxSs_SetCallBack(), and XDPRXSS_TMRCTR_RST_VAL.

Referenced by DpRxSs_DebugExample(), DpRxSs_HdcpExample(), DpRxSs_IntrExample(), DpRxSs_Main(), DpRxSs_MstExample(), and DpRxSs_SelfTestExample().

u32 XDpRxSs_CheckLinkStatus ( XDpRxSs * InstancePtr )

This function checks if the receiver's DisplayPort Configuration Data (DPCD) indicates that the receiver has achieved clock recovery, channel equalization, symbol lock, and interlane alignment for all lanes currently in use.

Parameters

InstancePtr is a pointer to the XDpRxSs core instance.

Returns

XST_SUCCESS if the RX device has achieved clock recovery, channel equalization, symbol lock, and interlane alignment.
XST_DEVICE_NOT_FOUND if no RX device is connected.
XST_FAILURE otherwise.

Note: None.

References XDpRxSs::DpPtr.

void XDpRxSs_DpIntrHandler ( void * InstancePtr )

This function is the interrupt handler for the DisplayPort RX core operating in RX mode.

The application is responsible for connecting this function to the interrupt system. Application beyond this driver is also responsible for providing callbacks to handle interrupts and installing the callbacks using XDpRxSs_SetCallBack() during initialization phase.

Parameters

InstancePtr is a pointer to the XDpRxSs core instance that just interrupted.

Note: None.

References XDpRxSs::DpPtr, and XDpRxSs::IsReady.

Referenced by DpRxSs_SetupIntrSystem().

void XDpRxSs_DrvNoVideoHandler ( void * InstancePtr )

This function is the interrupt handler for No Video.

Parameters

InstancePtr is a pointer to the XDpRxSs core instance that just interrupted.

Note: None.

References XDpRxSs::DpPtr, and XDpRxSs::IsReady.

Referenced by XDpRxSs_CfgInitialize().

void XDpRxSs_DrvPowerChangeHandler ( void * InstancePtr )

This function is for the power change interrupt handler.

Parameters

InstancePtr is a pointer to the XDpRxSs core instance that just interrupted.

Note: None.

References XDpRxSs::DpPtr, and XDpRxSs::IsReady.

Referenced by XDpRxSs_CfgInitialize().

void XDpRxSs_DrvVideoHandler ( void * InstancePtr )

This function is for the video interrupt handler.

Parameters

InstancePtr is a pointer to the XDpRxSs core instance that just interrupted.

Note: None.

References XDpRxSs::DpPtr, and XDpRxSs::IsReady.

Referenced by XDpRxSs_CfgInitialize().

u32 XDpRxSs_ExposePort	(	XDpRxSs *	InstancePtr,
		u8	Port
	)

This function allows the user to select number of ports to be exposed when replying to a LINK_ADDRESS sideband message and hides rest of the ports.

Parameters

InstancePtr	is a pointer to the XDpRxSs core instance.
Port	specifies the number of ports to be exposed within the range 1 to 4.

Returns

XST_SUCCESS, if ports exposed successfully.
XST_FAILURE, if exposing ports which are already exposed or ports are exceeding total number of stream supported by the system.

Note: Number of ports are equal to number of streams.

References XDpRxSs::Config, XDpRxSs::DpPtr, XDpRxSs_UsrOpt::MstSupport, XDpRxSs_Config::NumMstStreams, XDpRxSs_UsrOpt::NumOfStreams, and XDpRxSs::UsrOpt.

int XDpRxSs_Get_Dec_Clk_Lock ( XDpRxSs * InstancePtr )

This function resets the Clock Wizard and waits for it to lock after the receiver decode clock has been reconfigured.

Parameters

InstancePtr is a pointer to the XDpRxSs core instance.

Returns

XST_SUCCESS if the Clock Wizard locked successfully.
XST_FAILURE if the Clock Wizard failed to lock within the retry limit.

Note: None.

References XCLK_WIZ_STATUS_OFFSET, XCLK_WIZ_STATUS_RETRY, XCLK_WIZ_STATUS_WAIT, XCLK_WIZ_SWRST_OFFSET, XCLK_WIZ_SWRST_VAL, XDpRxSs_ReadReg, and XDpRxSs_WriteReg.

u8 XDpRxss_GetBpc	(	XDpRxSs *	InstancePtr,
		u8	Stream
	)

This function extracts the bits per color from MISC0 or VSC SDP packet based on whether reception of colorimetry information through VSC SDP packets or through MISC registers of the stream.

Parameters

InstancePtr	is a pointer to the XDpRxSs core instance.
Stream	is the stream number to make the calculations for.

Returns: The bits per color for the stream.

Note: RX clock must be stable.

References XDpRxSs::DpPtr.

u8 XDpRxss_GetColorComponent	(	XDpRxSs *	InstancePtr,
		u8	Stream
	)

This function extracts the color component format from MISC0 or VSC SDP packet based on whether reception of colorimetry information through VSC SDP packets or through MISC registers of the stream.

Parameters

InstancePtr	is a pointer to the XDpRxSs core instance.
Stream	is the stream number to make the calculations for.

Returns: The color component for the stream.

Note: RX clock must be stable.

References XDpRxSs::DpPtr.

u8 XDpRxss_GetColorimetry	(	XDpRxSs *	InstancePtr,
		u8	Stream
	)

This function extracts the YCbCrColorimetry from MISC0 or VSC SDP packet based on whether reception of colorimetry information through VSC SDP packets or through MISC registers of the stream.

Parameters

InstancePtr	is a pointer to the XDpRxSs core instance.
Stream	is the stream number to make the calculations for.

Returns: The colorimetry format for the stream.

Note: RX clock must be stable.

References XDpRxSs::DpPtr.

u32 XDpRxSs_GetDrvIndex ( UINTPTR BaseAddress )

This function returns the Index number of config table using BaseAddress.

Parameters

Base	address of the instance

Returns: Index number of the config table

u8 XDpRxss_GetDynamicRange	(	XDpRxSs *	InstancePtr,
		u8	Stream
	)

This function extracts the dynamic range from MISC0 or VSC SDP packet based on whether reception of colorimetry information through VSC SDP packets or through MISC registers of the stream.

Parameters

InstancePtr	is a pointer to the XDpRxSs core instance.
Stream	is the stream number to make the calculations for.

Returns: The dynamic range value for the stream.

Note: RX clock must be stable.

References XDpRxSs::DpPtr.

int XDpRxSs_GetVblank	(	XDpRxSs *	InstancePtr,
		u8	Stream
	)

This function retrieves the current vblank value of the incoming video stream.

Parameters

InstancePtr	is a pointer to the XDpRxSs core instance.
Stream	Stream is the stream number to get the vblank.

Returns

The current vblank value

Note: This function has to be called after assertion of Bit-30 of XDP_RX_INTERRUPT_CAUSE_2 register

References XDpRxSs::DpPtr, and XDpRxSs_ReadReg.

int XDpRxSs_GetVtotal	(	XDpRxSs *	InstancePtr,
		u8	Stream
	)

This function retrieves the current VTotal value of the incoming video stream.

Parameters

InstancePtr	is a pointer to the XDpRxSs core instance.
Stream	Stream is the stream number to get the vtotal.

Note: This function has to be called after assertion Bit-30 of XDP_RX_INTERRUPT_CAUSE_2 register

Returns

The current VTotal value

Note: This function has to be called after assertion of Bit-30 of XDP_RX_INTERRUPT_CAUSE_2 register

References XDpRxSs::DpPtr, and XDpRxSs_ReadReg.

u32 XDpRxSs_HandleDownReq ( XDpRxSs * InstancePtr )

This function handles incoming sideband messages.

It will 1) Read the contents of the down request registers, 2) Delegate control depending on the request type, and 3) Send a down reply.

Parameters

InstancePtr is a pointer to the XDpRxSs core instance.

Returns

XST_SUCCESS if the entire message was sent successfully.
XST_DEVICE_NOT_FOUND if no device is connected.
XST_ERROR_COUNT_MAX if sending one of the message fragments timed out.
XST_FAILURE otherwise.

Note: None.

References XDpRxSs::DpPtr.

Referenced by DpRxSs_DownReqestHandler().

XDpRxSs_Config * XDpRxSs_LookupConfig ( UINTPTR BaseAddress )

This function returns a reference to an XDpRxSs_Config structure based on the core id, DeviceId.

The return value will refer to an entry in the device configuration table defined in the xdprxss_g.c file.

Parameters

DeviceId is the unique core ID of the XDpRxSs core for the lookup operation.

Returns: XDpRxSs_LookupConfig returns a reference to a config record in the configuration table (in xdprxss_g.c) corresponding to DeviceId, or NULL if no match is found.

Note: None.

Referenced by DpRxSs_DebugExample(), DpRxSs_HdcpExample(), DpRxSs_IntrExample(), DpRxSs_Main(), DpRxSs_MstExample(), and DpRxSs_SelfTestExample().

void XDpRxSs_MaskAdaptiveIntr	(	XDpRxSs *	InstancePtr,
		u32	Mask
	)

This function masks the Adaptive-Sync interrupts from DisplayPort RX Subsystem.

Parameters

InstancePtr	is a pointer to the XDpRxSs instance.
Mask	Interrupts to mask

Note: None.

References XDpRxSs::DpPtr, XDpRxSs_ReadReg, and XDpRxSs_WriteReg.

int XDpRxSs_MCDP6000_AccessLaneSet	(	XDpRxSs *	DpRxSsPtr,
		u8	I2CSlaveAddress
	)

This function sets the access lane register of the MCDP6000 device.

Parameters

DpRxSsPtr	is a pointer to the XDpRxSs core instance.
I2CSlaveAddress	is the 7-bit I2C slave address.

Returns

XST_SUCCESS access lane set successful.
XST_FAILURE setting access lane failed.

Note: None.

References XDpRxSs_MCDP6000_SetRegister().

int XDpRxSs_MCDP6000_BWchange	(	XDpRxSs *	DpRxSsPtr,
		u8	I2CSlaveAddress
	)

This function changes the bandwidth of the MCDP6000 device.

Parameters

DpRxSsPtr	is a pointer to the XDpRxSs core instance.
I2CSlaveAddress	is the 7-bit I2C slave address.

Returns

XST_SUCCESS BW change successful.
XST_FAILURE BW change failed.

Note: None.

References XDpRxSs_MCDP6000_ModifyRegister().

int XDpRxSs_MCDP6000_ClearCounter	(	XDpRxSs *	DpRxSsPtr,
		u8	I2CSlaveAddress
	)

This function clears symbol counter.

Parameters

DpRxSsPtr	is a pointer to the XDpRxSs core instance.
I2CSlaveAddress	is the 7-bit I2C slave address.

Returns

XST_SUCCESS Enable request was successful.
XST_FAILURE I2C error.

Note: None.

References XDpRxSs_MCDP6000_GetRegister(), and XDpRxSs_MCDP6000_SetRegister().

Referenced by DpRxSs_AccessLinkQualHandler().

int XDpRxSs_MCDP6000_DisablePrbs7_Rx	(	XDpRxSs *	DpRxSsPtr,
		u8	I2CSlaveAddress
	)

This function Disables the PRBS7 counter mode in MC Rx path Used in DP PHY compliance mode.

Parameters

DpRxSsPtr	is a pointer to the XDpRxSs core instance.
I2CSlaveAddress	is the 7-bit I2C slave address.

Returns

XST_SUCCESS Enable request was successful.
XST_FAILURE I2C error.

Note: None.

References XDpRxSs_MCDP6000_GetRegister(), and XDpRxSs_MCDP6000_SetRegister().

Referenced by DpRxSs_AccessLinkQualHandler().

int XDpRxSs_MCDP6000_DpInit	(	XDpRxSs *	DpRxSsPtr,
		u8	I2CSlaveAddress
	)

This function initializes the MCDP6000 device with default values for DP use with the Video FMC.

Parameters

DpRxSsPtr	is a pointer to the XDpRxSs core instance.
I2CSlaveAddress	is the 7-bit I2C slave address.

Returns

XST_SUCCESS Initialization was successful.
XST_FAILURE I2C write error.

Note: None.

References XDpRxSs_MCDP6000_GetRegister(), and XDpRxSs_MCDP6000_SetRegister().

Referenced by XDpRxSs_McDp6000_init().

int XDpRxSs_MCDP6000_EnableCounter	(	XDpRxSs *	DpRxSsPtr,
		u8	I2CSlaveAddress
	)

This function enables symbol counter.

Parameters

DpRxSsPtr	is a pointer to the XDpRxSs core instance.
I2CSlaveAddress	is the 7-bit I2C slave address.

Returns

XST_SUCCESS Enable request was successful.
XST_FAILURE I2C error.

Note: None.

References XDpRxSs_MCDP6000_GetRegister(), and XDpRxSs_MCDP6000_SetRegister().

int XDpRxSs_MCDP6000_EnablePrbs7_Rx	(	XDpRxSs *	DpRxSsPtr,
		u8	I2CSlaveAddress
	)

This function enables the PRBS7 counter mode in MC Rx path Used in DP PHY compliance mode.

Parameters

DpRxSsPtr	is a pointer to the XDpRxSs core instance.
I2CSlaveAddress	is the 7-bit I2C slave address.

Returns

XST_SUCCESS Enable request was successful.
XST_FAILURE I2C error.

Note: None.

References XDpRxSs_MCDP6000_GetRegister(), and XDpRxSs_MCDP6000_SetRegister().

Referenced by DpRxSs_AccessLinkQualHandler().

int XDpRxSs_MCDP6000_EnablePrbs7_Tx	(	XDpRxSs *	DpRxSsPtr,
		u8	I2CSlaveAddress
	)

This function enables the PRBS7 output of the MCDP6000 device.

Parameters

DpRxSsPtr	is a pointer to the XDpRxSs core instance.
I2CSlaveAddress	is the 7-bit I2C slave address.

Returns

XST_SUCCESS Enable request was successful.
XST_FAILURE I2C error.

Note: None.

References XDpRxSs_MCDP6000_SetRegister().

u32 XDpRxSs_MCDP6000_GetRegister	(	XDpRxSs *	DpRxSsPtr,
		u8	I2CSlaveAddress,
		u16	RegisterAddress
	)

This function reads a single 32b word from the MCDP6000 device.

Parameters

DpRxSsPtr	is a pointer to the XDpRxSs core instance.
I2CSlaveAddress	is the 7-bit I2C slave address.
RegisterAddress	is the 16-bit register address.

Returns

The read 32b data.

Note: None.

References XDpRxSs::Config.

Referenced by DpRxSs_AccessErrorCounterHandler(), DpRxSs_Main(), XDpRxSs_MCDP6000_ClearCounter(), XDpRxSs_MCDP6000_DisablePrbs7_Rx(), XDpRxSs_MCDP6000_DpInit(), XDpRxSs_MCDP6000_EnableCounter(), XDpRxSs_MCDP6000_EnablePrbs7_Rx(), XDpRxSs_MCDP6000_ModifyRegister(), XDpRxSs_MCDP6000_Read_ErrorCounters(), and XDpRxSs_MCDP6000_RegisterDump().

int XDpRxSs_MCDP6000_IbertInit	(	XDpRxSs *	DpRxSsPtr,
		u8	I2CSlaveAddress
	)

This function initializes the MCDP6000 device with default values for IBERT use with the Video FMC.

Parameters

DpRxSsPtr	is a pointer to the XDpRxSs core instance.
I2CSlaveAddress	is the 7-bit I2C slave address.

Returns

XST_SUCCESS Initialization was successful.
XST_FAILURE I2C write error.

Note: None.

References XDpRxSs_MCDP6000_SetRegister().

void XDpRxSs_McDp6000_init ( void * InstancePtr )

This routine initializes the MCDP6000 part on the VFMC card used for DP 1.4.

Parameters

InstancePtr is a pointer to the XDpRxSs core instance.

Note: None.

References XDpRxSs_MCDP6000_DpInit(), and XDPRXSS_MCDP6000_IIC_SLAVE.

Referenced by DpRxSs_Main().

int XDpRxSs_MCDP6000_ModifyRegister	(	XDpRxSs *	DpRxSsPtr,
		u8	I2CSlaveAddress,
		u16	RegisterAddress,
		u32	Value,
		u32	Mask
	)

This function modifies a single 32b word from the MCDP6000 device.

Parameters

DpRxSsPtr	is a pointer to the XDpRxSs core instance.
I2CSlaveAddress	is the 7-bit I2C slave address.
RegisterAddress	is the 16-bit register address.
Value	is the 32b word to write
Mask	is the 32b mask

Returns

XST_SUCCESS Modification was successful.
XST_FAILURE I2C write error.

Note: None.

References XDpRxSs_MCDP6000_GetRegister(), and XDpRxSs_MCDP6000_SetRegister().

Referenced by XDpRxSs_MCDP6000_BWchange(), and XDpRxSs_MCDP6000_ResetCrPath().

int XDpRxSs_MCDP6000_Read_ErrorCounters	(	XDpRxSs *	DpRxSsPtr,
		u8	I2CSlaveAddress
	)

This function reads error counters for all lanes.

Parameters

DpRxSsPtr	is a pointer to the XDpRxSs core instance.
I2CSlaveAddress	is the 7-bit I2C slave address.

Returns

XST_SUCCESS Enable request was successful.
XST_FAILURE I2C error.

Note: None.

References XDpRxSs_MCDP6000_GetRegister(), and XDpRxSs_MCDP6000_SetRegister().

Referenced by DpRxSs_AccessErrorCounterHandler(), and DpRxSs_Main().

void XDpRxSs_MCDP6000_RegisterDump	(	XDpRxSs *	DpRxSsPtr,
		u8	I2CSlaveAddress
	)

This function displays a registerdump of the MCDP6000 device.

Parameters

DpRxSsPtr	is a pointer to the XDpRxSs core instance.
I2CSlaveAddress	is the 7-bit I2C slave address.

Note: None.

References XDpRxSs_MCDP6000_GetRegister().

int XDpRxSs_MCDP6000_ResetCrPath	(	XDpRxSs *	DpRxSsPtr,
		u8	I2CSlaveAddress
	)

This function requests a reset of the CR path of the MCDP6000 device.

Parameters

DpRxSsPtr	is a pointer to the XDpRxSs core instance.
I2CSlaveAddress	is the 7-bit I2C slave address.

Returns

XST_SUCCESS Reset request was successful.
XST_FAILURE I2C error.

Note: None.

References XDpRxSs_MCDP6000_ModifyRegister().

int XDpRxSs_MCDP6000_ResetDpPath	(	XDpRxSs *	DpRxSsPtr,
		u8	I2CSlaveAddress
	)

This function requests a reset of the DP path of the MCDP6000 device.

Parameters

DpRxSsPtr	is a pointer to the XDpRxSs core instance.
I2CSlaveAddress	is the 7-bit I2C slave address.

Returns

XST_SUCCESS Reset request was successful.
XST_FAILURE I2C error.

Note: None.

References XDpRxSs_MCDP6000_SetRegister().

int XDpRxSs_MCDP6000_SetRegister	(	XDpRxSs *	DpRxSsPtr,
		u8	I2CSlaveAddress,
		u16	RegisterAddress,
		u32	Value
	)

This function writes a single 32b word to the MCDP6000 device.

Parameters

DpRxSsPtr	is a pointer to the XDpRxSs core instance.
I2CSlaveAddress	is the 7-bit I2C slave address.
RegisterAddress	is the 16-bit register address.
Value	is the 32b word to write

Returns

XST_SUCCESS Register write was successful.
XST_FAILURE I2C write error.

Note: None.

References XDpRxSs::Config.

Referenced by XDpRxSs_MCDP6000_AccessLaneSet(), XDpRxSs_MCDP6000_ClearCounter(), XDpRxSs_MCDP6000_DisablePrbs7_Rx(), XDpRxSs_MCDP6000_DpInit(), XDpRxSs_MCDP6000_EnableCounter(), XDpRxSs_MCDP6000_EnablePrbs7_Rx(), XDpRxSs_MCDP6000_EnablePrbs7_Tx(), XDpRxSs_MCDP6000_IbertInit(), XDpRxSs_MCDP6000_ModifyRegister(), XDpRxSs_MCDP6000_Read_ErrorCounters(), XDpRxSs_MCDP6000_ResetDpPath(), and XDpRxSs_MCDP6000_TransparentMode().

int XDpRxSs_MCDP6000_TransparentMode	(	XDpRxSs *	DpRxSsPtr,
		u8	I2CSlaveAddress
	)

This function sets the transparent mode of the MCDP6000 device.

Parameters

DpRxSsPtr	is a pointer to the XDpRxSs core instance.
I2CSlaveAddress	is the 7-bit I2C slave address.

Returns

XST_SUCCESS transparent mode was set.
XST_FAILURE setting transparent mode failed.

Note: None.

References XDpRxSs_MCDP6000_SetRegister().

void XDpRxSs_ReportCoreInfo ( XDpRxSs * InstancePtr )

This function reports list of sub-cores included in DisplayPort RX Subsystem.

Parameters

InstancePtr is a pointer to the XDpRxSs core instance.

Note: None.

References XDpRxSs_Config::ColorFormat, XDpRxSs::Config, XDpRxSs::DpPtr, XDpRxSs_Config::HdcpEnable, XDpRxSs_Config::MaxBpc, XDpRxSs_Config::MaxLaneCount, XDpRxSs_Config::MaxNumAudioCh, XDpRxSs_UsrOpt::MstSupport, XDpRxSs_Config::MstSupport, XDpRxSs_Config::NumMstStreams, XDpRxSs_UsrOpt::NumOfStreams, XDpRxSs_Config::SecondaryChEn, and XDpRxSs::UsrOpt.

Referenced by DpRxSs_DebugExample(), and DpRxSs_Main().

void XDpRxSs_ReportHdcpInfo ( XDpRxSs * InstancePtr )

This function prints the debug display info of the HDCP interface.

Parameters

InstancePtr is a pointer to the XDpRxSs core instance.

Note: None.

Referenced by DpRxSs_DebugExample().

void XDpRxSs_ReportLinkInfo ( XDpRxSs * InstancePtr )

This function prints the link status, selected resolution, link rate /lane count symbol error.

Parameters

InstancePtr is a pointer to the XDpRxSs core instance.

Note: None.

References XDpRxSs::DpPtr, and XDpRxSs_ReadReg.

Referenced by DpRxSs_DebugExample(), and DpRxSs_Main().

void XDpRxSs_ReportMsaInfo ( XDpRxSs * InstancePtr )

This function prints the current main stream attributes from the DisplayPort RX core.

Parameters

InstancePtr is a pointer to the XDpRxSs core instance.

Note: None.

References XDpRxSs::Config, XDpRxSs::DpPtr, and XDpRxSs_Config::NumMstStreams.

Referenced by DpRxSs_DebugExample(), and DpRxSs_Main().

void XDpRxSs_Reset ( XDpRxSs * InstancePtr )

This function resets the DisplayPort Receiver Subsystem including all sub-cores.

Parameters

InstancePtr is a pointer to the XDpRxSs core instance.

Note: IIC needs to be reinitialized after reset.

References XDpRxSs::Config, XDpRxSs::DpPtr, XDpRxSs_Config::HdcpEnable, and XDpRxSs_WriteReg.

u32 XDpRxSs_SelfTest ( XDpRxSs * InstancePtr )

This function performs self test on DisplayPort Receiver Subsystem sub-cores.

Parameters

InstancePtr is a pointer to the XDpRxSs core instance.

Returns

XST_SUCCESS if self test passed.
Otherwise, prints self test failed message.

Note: None.

References XDpRxSs::Config, XDpRxSs::DpPtr, and XDpRxSs_Config::HdcpEnable.

Referenced by DpRxSs_SelfTestExample().

void XDpRxSs_SetAdaptiveSyncCaps	(	XDpRxSs *	InstancePtr,
		u32	Enable
	)

This function sets Adaptive-Sync capabilities to DisplayPort RX Subsystem.

Parameters

InstancePtr	is a pointer to the XDpRxSs instance.
Enable	is to enable/disable the Adaptive-Sync capabilities in DisplayPort Rx Subsystem

Note: None.

References XDpRxSs::DpPtr, XDpRxSs_ReadReg, and XDpRxSs_WriteReg.

u32 XDpRxSs_SetCallBack	(	XDpRxSs *	InstancePtr,
		u32	HandlerType,
		void *	CallbackFunc,
		void *	CallbackRef
	)

This function installs an asynchronous callback function for the given HandlerType:

HandlerType                              Callback Function Type
---------------------------------------- -----------------------------------
XDPRXSS_HANDLER_DP_VM_CHG_EVENT          XDp_RxSetIntrVmChangeHandler
XDPRXSS_HANDLER_DP_PWR_CHG_EVENT         XDp_RxSetIntrPowerStateHandler
XDPRXSS_HANDLER_DP_NO_VID_EVENT          XDp_RxSetIntrNoVideoHandler
XDPRXSS_HANDLER_DP_VBLANK_EVENT          XDp_RxSetIntrVBlankHandler
XDPRXSS_HANDLER_DP_TLOST_EVENT           XDp_RxSetIntrTrainingLostHandler
XDPRXSS_HANDLER_DP_VID_EVENT             XDp_RxSetIntrVideoHandler
XDPRXSS_HANDLER_DP_INFO_PKT_EVENT        XDp_RxSetIntrInfoPktHandler
XDPRXSS_HANDLER_DP_EXT_PKT_EVENT         XDp_RxSetIntrExtPktHandler
XDPRXSS_HANDLER_DP_TDONE_EVENT           XDp_RxSetIntrTrainingDoneHandler
XDPRXSS_HANDLER_DP_BW_CHG_EVENT          XDp_RxSetIntrBwChangeHandler
XDPRXSS_HANDLER_DP_DWN_REQ_EVENT         XDp_RxSetIntrDownReqHandler
XDPRXSS_HANDLER_DP_DWN_REP_EVENT         XDp_RxSetIntrDownReplyHandler
XDPRXSS_HANDLER_DP_AUD_OVRFLW_EVENT      XDp_RxSetIntrAudioOverHandler
XDPRXSS_HANDLER_DP_PAYLOAD_ALLOC_EVENT   XDp_RxSetIntrPayloadAllocHandler
XDPRXSS_HANDLER_DP_ACT_RX_EVENT          XDp_RxSetIntrActRxHandler
XDPRXSS_HANDLER_DP_CRC_TEST_EVENT        XDp_RxSetIntrCrcTestHandler
XDPRXSS_HANDLER_HDCP_RPTR_TDSA_EVENT     XHdcp1x_SetCallBack
XDPRXSS_HANDLER_UNPLUG_EVENT             UnplugCallback
XDPRXSS_HANDLER_LINKBW_EVENT             LinkBwCallback
XDPRXSS_HANDLER_PLL_RESET_EVENT          PllResetCallback

Parameters

InstancePtr	is a pointer to the XDpRxSs core instance.
HandlerType	specifies the type of handler.
CallbackFunc	is the address of the callback function.
CallbackRef	is a user data item that will be passed to the callback function when it is invoked.

Returns

XST_SUCCESS if callback function installed successfully.
XST_INVALID_PARAM when HandlerType is invalid.

Note: Invoking this function for a handler that already has been installed replaces it with the new handler.

Referenced by DpRxSs_SetupIntrSystem(), and XDpRxSs_CfgInitialize().

u32 XDpRxSs_SetLaneCount	(	XDpRxSs *	InstancePtr,
		u8	LaneCount
	)

This function sets the number of lanes to be used by DisplayPort RX Subsystem core.

Parameters

InstancePtr	is a pointer to the XDpRxSs instance.
LaneCount	is the number of lanes to be used. 1 = XDPRXSS_LANE_COUNT_SET_1 2 = XDPRXSS_LANE_COUNT_SET_2 4 = XDPRXSS_LANE_COUNT_SET_4

Returns

XST_SUCCESS if setting the new lane count was successful.
XST_FAILURE otherwise.

Note: None.

References XDpRxSs::DpPtr, XDpRxSs_UsrOpt::LaneCount, XDpRxSs::UsrOpt, XDPRXSS_LANE_COUNT_SET_1, XDPRXSS_LANE_COUNT_SET_2, and XDPRXSS_LANE_COUNT_SET_4.

Referenced by DpRxSs_DebugExample(), DpRxSs_HdcpExample(), DpRxSs_IntrExample(), DpRxSs_Main(), and DpRxSs_MstExample().

u32 XDpRxSs_SetLinkRate	(	XDpRxSs *	InstancePtr,
		u8	LinkRate
	)

This function sets the data rate to be used by the DisplayPort RX Subsystem core.

Parameters

InstancePtr	is a pointer to the XDpRxSs instance.
LinkRate	is the rate at which link needs to be driven. XDPRXSS_LINK_BW_SET_162GBPS = 0x06(for a 1.62 Gbps data rate) XDPRXSS_LINK_BW_SET_270GBPS = 0x0A(for a 2.70 Gbps data rate) XDPRXSS_LINK_BW_SET_540GBPS = 0x14(for a 5.40 Gbps data rate)

Returns

XST_SUCCESS if setting the new lane rate was successful.
XST_FAILURE otherwise.

Note: None.

References XDpRxSs::DpPtr, XDpRxSs_UsrOpt::LinkRate, XDpRxSs::UsrOpt, XDPRXSS_LINK_BW_SET_162GBPS, XDPRXSS_LINK_BW_SET_270GBPS, XDPRXSS_LINK_BW_SET_540GBPS, and XDPRXSS_LINK_BW_SET_810GBPS.

Referenced by DpRxSs_DebugExample(), DpRxSs_HdcpExample(), DpRxSs_IntrExample(), DpRxSs_Main(), and DpRxSs_MstExample().

void XDpRxSs_SetUserPixelWidth	(	XDpRxSs *	InstancePtr,
		u8	UserPixelWidth
	)

This function configures the number of pixels output through the user data interface.

Parameters

InstancePtr	is a pointer to the XDpRxSs core instance.
UserPixelWidth	is the user pixel width to be configured.

Note: None.

References XDpRxSs::DpPtr.

void XDpRxSs_SetUserTimerHandler	(	XDpRxSs *	InstancePtr,
		XDpRxSs_TimerHandler	CallbackFunc,
		void *	CallbackRef
	)

This function installs a custom delay/sleep function to be used by the DisplayPort RX Subsystem.

Parameters

InstancePtr	is a pointer to the XDpRxSs core instance.
CallbackFunc	is the address to the callback function.
CallbackRef	is the user data item (microseconds to delay) that will be passed to the custom sleep/delay function when it is invoked.

Note: None.

References XDpRxSs::DpPtr.

Referenced by DpRxSs_SetupIntrSystem(), and DpRxSs_SetupTimerHandler().

u32 XDpRxSs_Start ( XDpRxSs * InstancePtr )

This function starts the DisplayPort Receiver Subsystem including all sub-cores.

Parameters

InstancePtr is a pointer to the XDpRxSs core instance.

Returns

XST_SUCCESS, if DP RX Subsystem and its included sub-cores configured successfully.
XST_FAILURE, otherwise.

Note: None.

References XDpRxSs::DpPtr, XDpRxSs_UsrOpt::MstSupport, and XDpRxSs::UsrOpt.

Referenced by DpRxSs_DebugExample(), DpRxSs_HdcpExample(), DpRxSs_IntrExample(), DpRxSs_Main(), and DpRxSs_MstExample().

void XDpRxSs_UnMaskAdaptiveIntr	(	XDpRxSs *	InstancePtr,
		u32	Mask
	)

This function unmasks Adaptive-Sync interrupt from DisplayPort RX Subsystem.

Parameters

InstancePtr	is a pointer to the XDpRxSs instance.
Mask	Interrupts to unmask

Note: None.

References XDpRxSs::DpPtr, XDpRxSs_ReadReg, and XDpRxSs_WriteReg.

Variable Documentation

XDpRxSs_SubCores DpRxSsSubCores[XPAR_XDPRXSS_NUM_INSTANCES]

DisplayPort RX subcores instance array.

This array contains the subcore configuration for all DisplayPort RX subsystem instances.

u8 GenDpcd[]

Initial value:

= {
        0x12, 0x0a, 0x84, 0x01, 0x01, 0x00, 0x00, 0x00, 0x02
}

A generic DPCD (DisplayPort Configuration Data) structure.

This array contains default DPCD register values.

u8 GenEdid[128]

Initial value:

= {
        0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
        0x61, 0x2c, 0x01, 0x00, 0x78, 0x56, 0x34, 0x12,
        0x01, 0x18, 0x01, 0x04, 0xa0, 0x2f, 0x1e, 0x78,
        0x00, 0xee, 0x95, 0xa3, 0x54, 0x4c, 0x99, 0x26,
        0x0f, 0x50, 0x54, 0x21, 0x08, 0x00, 0x71, 0x4f,
        0x81, 0x80, 0xb3, 0x00, 0xd1, 0xc0, 0x01, 0x01,
        0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x3a,
        0x80, 0x18, 0x71, 0x38, 0x2d, 0x40, 0x58, 0x2c,
        0x45, 0x00, 0x40, 0x84, 0x63, 0x00, 0x00, 0x1e,
        0x00, 0x00, 0x00, 0xff, 0x00, 0x58, 0x49, 0x4c,
        0x44, 0x50, 0x53, 0x49, 0x4e, 0x4b, 0x0a, 0x20,
        0x20, 0x20, 0x00, 0x00, 0x00, 0xfc, 0x00, 0x58,
        0x49, 0x4c, 0x20, 0x44, 0x50, 0x0a, 0x20, 0x20,
        0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xfd,
        0x00, 0x38, 0x3c, 0x1e, 0x53, 0x10, 0x00, 0x0a,
        0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x00, 0x39
}

A generic EDID (Extended Display Identification Data) structure.

This array contains a default 128-byte EDID configuration for display capability.

Data Structures

Macros

Typedefs

Enumerations

Functions

Clock Wizard register offsets and default values

CLKx5 Wizard per-link-rate configuration values

Clock Wizard control bit masks and shift values

MMCM multiplier and divider values

Register access macro definition

Macro Definition Documentation

Typedef Documentation

Enumeration Type Documentation

Function Documentation

Variable Documentation