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vphy
Vitis Drivers API Documentation
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vphy
Vitis Drivers API Documentation
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This header file contains the identifiers and low-level driver functions (or macros) that can be used to access the device.
High-level driver functions are defined in xvphy.h.
MODIFICATION HISTORY:
Ver Who Date Changes
1.0 als 10/19/15 Initial release. 1.1 gm 02/01/16 Added GTPE2 and GTHE4 support 1.4 gm 29/11/16 Added ERR_IRQ register offset 1.5 gm 02/05/17 Added CPLL CAL reg and corresponding masks 1.6 gm 06/08/17 Added TX and RX MMCM lock Masks 1.7 gm 13/09/17 Added GTYE4 support
#include "xil_io.h"#include "xil_types.h"Macros | |
| #define | XVphy_ReadReg(BaseAddress, RegOffset) XVphy_In32((BaseAddress) + (RegOffset)) |
| This is a low-level function that reads from the specified register. More... | |
| #define | XVphy_WriteReg(BaseAddress, RegOffset, Data) XVphy_Out32((BaseAddress) + (RegOffset), (Data)) |
| This is a low-level function that writes to the specified register. More... | |
VPHY core registers: General registers. | |
Address mapping for the Video PHY core. | |
| #define | XVPHY_VERSION_REG 0x000 |
| Version register offset. More... | |
| #define | XVPHY_BANK_SELECT_REG 0x00C |
| Bank select register offset. More... | |
| #define | XVPHY_REF_CLK_SEL_REG 0x010 |
| Reference clock select register offset. More... | |
| #define | XVPHY_PLL_RESET_REG 0x014 |
| PLL reset register offset. More... | |
| #define | XVPHY_PLL_LOCK_STATUS_REG 0x018 |
| PLL lock status register offset. More... | |
| #define | XVPHY_TX_INIT_REG 0x01C |
| TX init register offset. More... | |
| #define | XVPHY_TX_INIT_STATUS_REG 0x020 |
| TX init status register offset. More... | |
| #define | XVPHY_RX_INIT_REG 0x024 |
| RX init register offset. More... | |
| #define | XVPHY_RX_INIT_STATUS_REG 0x028 |
| RX init status register offset. More... | |
| #define | XVPHY_IBUFDS_GTXX_CTRL_REG 0x02C |
| IBUFDS GTXX control register offset. More... | |
| #define | XVPHY_POWERDOWN_CONTROL_REG 0x030 |
| Power down control register offset. More... | |
| #define | XVPHY_LOOPBACK_CONTROL_REG 0x038 |
| Loopback control register offset. More... | |
VPHY core registers: Dynamic reconfiguration port (DRP) registers. | |
| #define | XVPHY_DRP_CONTROL_CH1_REG 0x040 |
| DRP control channel 1 register offset. More... | |
| #define | XVPHY_DRP_CONTROL_CH2_REG 0x044 |
| DRP control channel 2 register offset. More... | |
| #define | XVPHY_DRP_CONTROL_CH3_REG 0x048 |
| DRP control channel 3 register offset. More... | |
| #define | XVPHY_DRP_CONTROL_CH4_REG 0x04C |
| DRP control channel 4 register offset. More... | |
| #define | XVPHY_DRP_STATUS_CH1_REG 0x050 |
| DRP status channel 1 register offset. More... | |
| #define | XVPHY_DRP_STATUS_CH2_REG 0x054 |
| DRP status channel 2 register offset. More... | |
| #define | XVPHY_DRP_STATUS_CH3_REG 0x058 |
| DRP status channel 3 register offset. More... | |
| #define | XVPHY_DRP_STATUS_CH4_REG 0x05C |
| DRP status channel 4 register offset. More... | |
| #define | XVPHY_DRP_CONTROL_COMMON_REG 0x060 |
| DRP control common register offset. More... | |
| #define | XVPHY_DRP_STATUS_COMMON_REG 0x064 |
| DRP status common register offset. More... | |
| #define | XVPHY_DRP_CONTROL_TXMMCM_REG 0x124 |
| DRP control TX MMCM register offset. More... | |
| #define | XVPHY_DRP_STATUS_TXMMCM_REG 0x128 |
| DRP status TX MMCM register offset. More... | |
| #define | XVPHY_DRP_CONTROL_RXMMCM_REG 0x144 |
| DRP control RX MMCM register offset. More... | |
| #define | XVPHY_DRP_STATUS_RXMMCM_REG 0x148 |
| DRP status RX MMCM register offset. More... | |
VPHY core registers: CPLL Calibration registers. | |
| #define | XVPHY_CPLL_CAL_PERIOD_REG 0x068 |
| CPLL calibration period register offset. More... | |
| #define | XVPHY_CPLL_CAL_TOL_REG 0x06C |
| CPLL calibration tolerance register offset. More... | |
VPHY core registers: Transmitter function registers. | |
| #define | XVPHY_TX_CONTROL_REG 0x070 |
| TX control register offset. More... | |
| #define | XVPHY_TX_BUFFER_BYPASS_REG 0x074 |
| TX buffer bypass register offset. More... | |
| #define | XVPHY_TX_STATUS_REG 0x078 |
| TX status register offset. More... | |
| #define | XVPHY_TX_DRIVER_CH12_REG 0x07C |
| TX driver channel 1-2 register offset. More... | |
| #define | XVPHY_TX_DRIVER_CH34_REG 0x080 |
| TX driver channel 3-4 register offset. More... | |
VPHY core registers: Receiver function registers. | |
| #define | XVPHY_RX_CONTROL_REG 0x100 |
| RX control register offset. More... | |
| #define | XVPHY_RX_STATUS_REG 0x104 |
| RX status register offset. More... | |
| #define | XVPHY_RX_EQ_CDR_REG 0x108 |
| RX EQ CDR register offset. More... | |
| #define | XVPHY_RX_TDLOCK_REG 0x10C |
| RX TD lock register offset. More... | |
VPHY core registers: Interrupt registers. | |
| #define | XVPHY_ERR_IRQ 0x03C |
| Error IRQ register offset. More... | |
| #define | XVPHY_INTR_EN_REG 0x110 |
| Interrupt enable register offset. More... | |
| #define | XVPHY_INTR_DIS_REG 0x114 |
| Interrupt disable register offset. More... | |
| #define | XVPHY_INTR_MASK_REG 0x118 |
| Interrupt mask register offset. More... | |
| #define | XVPHY_INTR_STS_REG 0x11C |
| Interrupt status register offset. More... | |
User clocking registers: MMCM and BUFGGT registers. | |
| #define | XVPHY_MMCM_TXUSRCLK_CTRL_REG 0x0120 |
| MMCM TX user clock control register offset. More... | |
| #define | XVPHY_MMCM_TXUSRCLK_REG1 0x0124 |
| MMCM TX user clock register 1 offset. More... | |
| #define | XVPHY_MMCM_TXUSRCLK_REG2 0x0128 |
| MMCM TX user clock register 2 offset. More... | |
| #define | XVPHY_MMCM_TXUSRCLK_REG3 0x012C |
| MMCM TX user clock register 3 offset. More... | |
| #define | XVPHY_MMCM_TXUSRCLK_REG4 0x0130 |
| MMCM TX user clock register 4 offset. More... | |
| #define | XVPHY_BUFGGT_TXUSRCLK_REG 0x0134 |
| BUFGGT TX user clock register offset. More... | |
| #define | XVPHY_MISC_TXUSRCLK_REG 0x0138 |
| Misc TX user clock register offset. More... | |
| #define | XVPHY_MMCM_RXUSRCLK_CTRL_REG 0x0140 |
| MMCM RX user clock control register offset. More... | |
| #define | XVPHY_MMCM_RXUSRCLK_REG1 0x0144 |
| MMCM RX user clock register 1 offset. More... | |
| #define | XVPHY_MMCM_RXUSRCLK_REG2 0x0148 |
| MMCM RX user clock register 2 offset. More... | |
| #define | XVPHY_MMCM_RXUSRCLK_REG3 0x014C |
| MMCM RX user clock register 3 offset. More... | |
| #define | XVPHY_MMCM_RXUSRCLK_REG4 0x0150 |
| MMCM RX user clock register 4 offset. More... | |
| #define | XVPHY_BUFGGT_RXUSRCLK_REG 0x0154 |
| BUFGGT RX user clock register offset. More... | |
| #define | XVPHY_MISC_RXUSRCLK_REG 0x0158 |
| Misc RX user clock register offset. More... | |
Clock detector (HDMI) registers. | |
| #define | XVPHY_CLKDET_CTRL_REG 0x0200 |
| Clock detector control register offset. More... | |
| #define | XVPHY_CLKDET_STAT_REG 0x0204 |
| Clock detector status register offset. More... | |
| #define | XVPHY_CLKDET_FREQ_TMR_TO_REG 0x0208 |
| Clock detector frequency timer timeout register offset. More... | |
| #define | XVPHY_CLKDET_FREQ_TX_REG 0x020C |
| Clock detector TX frequency register offset. More... | |
| #define | XVPHY_CLKDET_FREQ_RX_REG 0x0210 |
| Clock detector RX frequency register offset. More... | |
| #define | XVPHY_CLKDET_TMR_TX_REG 0x0214 |
| Clock detector TX timer register offset. More... | |
| #define | XVPHY_CLKDET_TMR_RX_REG 0x0218 |
| Clock detector RX timer register offset. More... | |
| #define | XVPHY_CLKDET_FREQ_DRU_REG 0x021C |
| Clock detector DRU frequency register offset. More... | |
| #define | XVPHY_CLKDET_FREQ_TX_RAW_REG 0x0220 |
| Clock detector RAW TX frequency register offset. More... | |
| #define | XVPHY_CLKDET_FREQ_RX_RAW_REG 0x0224 |
| Clock detector RAW RX frequency register offset. More... | |
| #define | XVPHY_CLKDET_FREQ_DRU_RAW_REG 0x0228 |
| Clock detector RAW DRU frequency register offset. More... | |
Data recovery unit registers (HDMI). | |
| #define | XVPHY_DRU_CTRL_REG 0x0300 |
| DRU control register offset. More... | |
| #define | XVPHY_DRU_STAT_REG 0x0304 |
| DRU status register offset. More... | |
| #define | XVPHY_DRU_CFREQ_L_REG(Ch) (0x0308 + (12 * (Ch - 1))) |
| DRU center frequency low register offset. More... | |
| #define | XVPHY_DRU_CFREQ_H_REG(Ch) (0x030C + (12 * (Ch - 1))) |
| DRU center frequency high register offset. More... | |
| #define | XVPHY_DRU_GAIN_REG(Ch) (0x0310 + (12 * (Ch - 1))) |
| DRU gain register offset. More... | |
TMDS Clock Pattern Generator registers (HDMI). | |
| #define | XVPHY_PATGEN_CTRL_REG 0x0340 |
| Pattern generator control register offset. More... | |
VPHY core masks, shifts, and register values. | |
| #define | XVPHY_VERSION_INTER_REV_MASK 0x000000FF |
| Internal revision. More... | |
| #define | XVPHY_VERSION_CORE_PATCH_MASK 0x00000F00 |
| Core patch details. More... | |
| #define | XVPHY_VERSION_CORE_PATCH_SHIFT 8 |
| Shift bits for core patch details. More... | |
| #define | XVPHY_VERSION_CORE_VER_REV_MASK 0x0000F000 |
| Core version revision. More... | |
| #define | XVPHY_VERSION_CORE_VER_REV_SHIFT 12 |
| Shift bits for core version revision. More... | |
| #define | XVPHY_VERSION_CORE_VER_MNR_MASK 0x00FF0000 |
| Core minor version. More... | |
| #define | XVPHY_VERSION_CORE_VER_MNR_SHIFT 16 |
| Shift bits for core minor version. More... | |
| #define | XVPHY_VERSION_CORE_VER_MJR_MASK 0xFF000000 |
| Core major version. More... | |
| #define | XVPHY_VERSION_CORE_VER_MJR_SHIFT 24 |
| Shift bits for core major version. More... | |
0x00C: BANK_SELECT_REG masks and shifts. | |
| #define | XVPHY_BANK_SELECT_TX_MASK 0x00F |
| TX bank select mask. More... | |
| #define | XVPHY_BANK_SELECT_RX_MASK 0xF00 |
| RX bank select mask. More... | |
| #define | XVPHY_BANK_SELECT_RX_SHIFT 8 |
| RX bank select shift. More... | |
0x010: REF_CLK_SEL register masks and values. | |
| #define | XVPHY_REF_CLK_SEL_QPLL0_MASK 0x0000000F |
| QPLL0 refclk select mask. More... | |
| #define | XVPHY_REF_CLK_SEL_CPLL_MASK 0x000000F0 |
| CPLL refclk select mask. More... | |
| #define | XVPHY_REF_CLK_SEL_CPLL_SHIFT 4 |
| CPLL refclk select shift. More... | |
| #define | XVPHY_REF_CLK_SEL_QPLL1_MASK 0x00000F00 |
| QPLL1 refclk select mask. More... | |
| #define | XVPHY_REF_CLK_SEL_QPLL1_SHIFT 8 |
| QPLL1 refclk select shift. More... | |
| #define | XVPHY_REF_CLK_SEL_XPLL_GTREFCLK0 1 |
| GTREFCLK0 select value. More... | |
| #define | XVPHY_REF_CLK_SEL_XPLL_GTREFCLK1 2 |
| GTREFCLK1 select value. More... | |
| #define | XVPHY_REF_CLK_SEL_XPLL_GTNORTHREFCLK0 3 |
| GTNORTHREFCLK0 select value. More... | |
| #define | XVPHY_REF_CLK_SEL_XPLL_GTNORTHREFCLK1 4 |
| GTNORTHREFCLK1 select value. More... | |
| #define | XVPHY_REF_CLK_SEL_XPLL_GTSOUTHREFCLK0 5 |
| GTSOUTHREFCLK0 select value. More... | |
| #define | XVPHY_REF_CLK_SEL_XPLL_GTSOUTHREFCLK1 6 |
| GTSOUTHREFCLK1 select value. More... | |
| #define | XVPHY_REF_CLK_SEL_XPLL_GTEASTREFCLK0 3 |
| GTEASTREFCLK0 select value. More... | |
| #define | XVPHY_REF_CLK_SEL_XPLL_GTEASTREFCLK1 4 |
| GTEASTREFCLK1 select value. More... | |
| #define | XVPHY_REF_CLK_SEL_XPLL_GTWESTREFCLK0 5 |
| GTWESTREFCLK0 select value. More... | |
| #define | XVPHY_REF_CLK_SEL_XPLL_GTWESTREFCLK1 6 |
| GTWESTREFCLK1 select value. More... | |
| #define | XVPHY_REF_CLK_SEL_XPLL_GTGREFCLK 7 |
| GTGREFCLK select value. More... | |
| #define | XVPHY_REF_CLK_SEL_SYSCLKSEL_MASK 0x0F000000 |
| SYSCLKSEL mask. More... | |
| #define | XVPHY_REF_CLK_SEL_SYSCLKSEL_SHIFT 24 |
| SYSCLKSEL shift. More... | |
| #define | XVPHY_REF_CLK_SEL_XXSYSCLKSEL_DATA_PLL0 0 |
| SYSGLKSEL data PLL0 value. More... | |
| #define | XVPHY_REF_CLK_SEL_XXSYSCLKSEL_DATA_PLL1 1 |
| SYSCLKSEL data PLL1 value. More... | |
| #define | XVPHY_REF_CLK_SEL_XXSYSCLKSEL_DATA_CPLL 0 |
| SYSCLKSEL data CPLL value. More... | |
| #define | XVPHY_REF_CLK_SEL_XXSYSCLKSEL_DATA_QPLL 1 |
| SYSCLKSEL data QPLL value. More... | |
| #define | XVPHY_REF_CLK_SEL_XXSYSCLKSEL_DATA_QPLL0 3 |
| SYSCLKSEL data QPLL0 value. More... | |
| #define | XVPHY_REF_CLK_SEL_XXSYSCLKSEL_DATA_QPLL1 2 |
| SYSCLKSEL data QPLL1 value. More... | |
| #define | XVPHY_REF_CLK_SEL_XXSYSCLKSEL_OUT_CH 0 |
| SYSCLKSEL out channel value. More... | |
| #define | XVPHY_REF_CLK_SEL_XXSYSCLKSEL_OUT_CMN 1 |
| SYSCLKSEL out common value. More... | |
| #define | XVPHY_REF_CLK_SEL_XXSYSCLKSEL_OUT_CMN0 2 |
| SYSCLKSEL out CMN0 value. More... | |
| #define | XVPHY_REF_CLK_SEL_XXSYSCLKSEL_OUT_CMN1 3 |
| SYSCLKSEL out CMN1 value. More... | |
| #define | XVPHY_REF_CLK_SEL_RXSYSCLKSEL_OUT_MASK(G) |
| RX SYSCLKSEL out mask based on GT type. More... | |
| #define | XVPHY_REF_CLK_SEL_TXSYSCLKSEL_OUT_MASK(G) |
| TX SYSCLKSEL out mask based on GT type. More... | |
| #define | XVPHY_REF_CLK_SEL_RXSYSCLKSEL_DATA_MASK(G) |
| RX SYSCLKSEL data mask based on GT type. More... | |
| #define | XVPHY_REF_CLK_SEL_TXSYSCLKSEL_DATA_MASK(G) |
| TX SYSCLKSEL data mask based on GT type. More... | |
| #define | XVPHY_REF_CLK_SEL_RXSYSCLKSEL_OUT_SHIFT(G) |
| RX SYSCLKSEL out shift based on GT type. More... | |
| #define | XVPHY_REF_CLK_SEL_TXSYSCLKSEL_OUT_SHIFT(G) |
| TX SYSCLKSEL out shift based on GT type. More... | |
| #define | XVPHY_REF_CLK_SEL_RXSYSCLKSEL_DATA_SHIFT(G) |
| RX SYSCLKSEL data shift based on GT type. More... | |
| #define | XVPHY_REF_CLK_SEL_TXSYSCLKSEL_DATA_SHIFT(G) |
| TX SYSCLKSEL data shift based on GT type. More... | |
0x014: PLL_RESET register masks. | |
| #define | XVPHY_PLL_RESET_CPLL_MASK 0x1 |
| CPLL reset mask. More... | |
| #define | XVPHY_PLL_RESET_QPLL0_MASK 0x2 |
| QPLL0 reset mask. More... | |
| #define | XVPHY_PLL_RESET_QPLL1_MASK 0x4 |
| QPLL1 reset mask. More... | |
0x018: PLL_LOCK_STATUS register masks. | |
| #define | XVPHY_PLL_LOCK_STATUS_CPLL_MASK(Ch) (0x01 << (Ch - 1)) |
| CPLL lock status mask for channel. More... | |
| #define | XVPHY_PLL_LOCK_STATUS_QPLL0_MASK 0x10 |
| QPLL0 lock status mask. More... | |
| #define | XVPHY_PLL_LOCK_STATUS_QPLL1_MASK 0x20 |
| QPLL1 lock status mask. More... | |
| #define | XVPHY_PLL_LOCK_STATUS_CPLL_ALL_MASK |
| CPLL lock status mask for all channels. More... | |
| #define | XVPHY_PLL_LOCK_STATUS_CPLL_HDMI_MASK |
| CPLL lock status mask for HDMI channels. More... | |
0x01C, 0x024: TX_INIT, RX_INIT register masks. | |
| #define | XVPHY_TXRX_INIT_GTRESET_MASK(Ch) (0x01 << (8 * (Ch - 1))) |
| GT reset mask for channel. More... | |
| #define | XVPHY_TXRX_INIT_PMARESET_MASK(Ch) (0x02 << (8 * (Ch - 1))) |
| PMA reset mask for channel. More... | |
| #define | XVPHY_TXRX_INIT_PCSRESET_MASK(Ch) (0x04 << (8 * (Ch - 1))) |
| PCS reset mask for channel. More... | |
| #define | XVPHY_TX_INIT_USERRDY_MASK(Ch) (0x08 << (8 * (Ch - 1))) |
| TX user ready mask for channel. More... | |
| #define | XVPHY_RX_INIT_USERRDY_MASK(Ch) (0x40 << (8 * (Ch - 1))) |
| RX user ready mask for channel. More... | |
| #define | XVPHY_TXRX_INIT_PLLGTRESET_MASK(Ch) (0x80 << (8 * (Ch - 1))) |
| PLL GT reset mask for channel. More... | |
| #define | XVPHY_TXRX_INIT_GTRESET_ALL_MASK |
| GT reset mask for all channels. More... | |
| #define | XVPHY_TX_INIT_USERRDY_ALL_MASK |
| TX user ready mask for all channels. More... | |
| #define | XVPHY_RX_INIT_USERRDY_ALL_MASK |
| RX user ready mask for all channels. More... | |
| #define | XVPHY_TXRX_INIT_PLLGTRESET_ALL_MASK |
| PLL GT reset mask for all channels. More... | |
0x020, 0x028: TX_STATUS, RX_STATUS register masks. | |
| #define | XVPHY_TXRX_INIT_STATUS_RESETDONE_MASK(Ch) (0x01 << (8 * (Ch - 1))) |
| Reset done mask for channel. More... | |
| #define | XVPHY_TXRX_INIT_STATUS_PMARESETDONE_MASK(Ch) (0x02 << (8 * (Ch - 1))) |
| PMA reset done mask for channel. More... | |
| #define | XVPHY_TXRX_INIT_STATUS_POWERGOOD_MASK(Ch) (0x04 << (8 * (Ch - 1))) |
| Power good mask for channel. More... | |
| #define | XVPHY_TXRX_INIT_STATUS_RESETDONE_ALL_MASK |
| Reset done mask for all channels. More... | |
| #define | XVPHY_TXRX_INIT_STATUS_PMARESETDONE_ALL_MASK |
| PMA reset done mask for all channels. More... | |
0x02C: IBUFDS_GTXX_CTRL register masks. | |
| #define | XVPHY_IBUFDS_GTXX_CTRL_GTREFCLK0_CEB_MASK 0x1 |
| GTREFCLK0 CEB mask. More... | |
| #define | XVPHY_IBUFDS_GTXX_CTRL_GTREFCLK1_CEB_MASK 0x2 |
| GTREFCLK1 CEB mask. More... | |
0x030: POWERDOWN_CONTROL register masks. | |
| #define | XVPHY_POWERDOWN_CONTROL_CPLLPD_MASK(Ch) (0x01 << (8 * (Ch - 1))) |
| CPLL power down mask for channel. More... | |
| #define | XVPHY_POWERDOWN_CONTROL_QPLL0PD_MASK(Ch) (0x02 << (8 * (Ch - 1))) |
| QPLL0 power down mask for channel. More... | |
| #define | XVPHY_POWERDOWN_CONTROL_QPLL1PD_MASK(Ch) (0x04 << (8 * (Ch - 1))) |
| QPLL1 power down mask for channel. More... | |
| #define | XVPHY_POWERDOWN_CONTROL_RXPD_MASK(Ch) (0x18 << (8 * (Ch - 1))) |
| RX power down mask for channel. More... | |
| #define | XVPHY_POWERDOWN_CONTROL_RXPD_SHIFT(Ch) (3 + (8 * (Ch - 1))) |
| RX power down shift for channel. More... | |
| #define | XVPHY_POWERDOWN_CONTROL_TXPD_MASK(Ch) (0x60 << (8 * (Ch - 1))) |
| TX power down mask for channel. More... | |
| #define | XVPHY_POWERDOWN_CONTROL_TXPD_SHIFT(Ch) (5 + (8 * (Ch - 1))) |
| TX power down shift for channel. More... | |
0x038: LOOPBACK_CONTROL register masks. | |
| #define | XVPHY_LOOPBACK_CONTROL_CH_MASK(Ch) (0x03 << (8 * (Ch - 1))) |
| Loopback control mask for channel. More... | |
| #define | XVPHY_LOOPBACK_CONTROL_CH_SHIFT(Ch) (8 * (Ch - 1)) |
| Loopback control shift for channel. More... | |
Register access macro definitions. | |
| #define | XVphy_In32 Xil_In32 |
| Input operation macro for 32-bit reads. More... | |
| #define | XVphy_Out32 Xil_Out32 |
| Output operation macro for 32-bit writes. More... | |
| #define XVphy_In32 Xil_In32 |
Input operation macro for 32-bit reads.
| #define XVphy_Out32 Xil_Out32 |
Output operation macro for 32-bit writes.
| #define XVphy_ReadReg | ( | BaseAddress, | |
| RegOffset | |||
| ) | XVphy_In32((BaseAddress) + (RegOffset)) |
This is a low-level function that reads from the specified register.
| BaseAddress | is the base address of the device. |
| RegOffset | is the register offset to be read from. |
Referenced by XVphy_CfgErrIntr(), XVphy_Clkout1OBufTdsEnable(), XVphy_GetSysClkDataSel(), XVphy_GetSysClkOutSel(), XVphy_GetVersion(), XVphy_GtUserRdyEnable(), XVphy_IBufDsEnable(), XVphy_InterruptHandler(), XVphy_IntrDisable(), XVphy_IntrEnable(), XVphy_IsPllLocked(), XVphy_MmcmLocked(), XVphy_MmcmLockedMaskEnable(), XVphy_MmcmPowerDown(), XVphy_MmcmReset(), XVphy_PowerDownGtPll(), XVphy_RegisterDebug(), XVphy_ResetGtPll(), XVphy_ResetGtTxRx(), XVphy_SelfTest(), XVphy_SetBufgGtDiv(), XVphy_SetPolarity(), XVphy_SetPrbsSel(), XVphy_SetRxLpm(), XVphy_SetTxPostCursor(), XVphy_SetTxPreEmphasis(), XVphy_SetTxVoltageSwing(), and XVphy_TxPrbsForceError().
| #define XVphy_WriteReg | ( | BaseAddress, | |
| RegOffset, | |||
| Data | |||
| ) | XVphy_Out32((BaseAddress) + (RegOffset), (Data)) |
This is a low-level function that writes to the specified register.
| BaseAddress | is the base address of the device. |
| RegOffset | is the register offset to write to. |
| Data | is the 32-bit data to write to the specified register. |
Referenced by XVphy_CfgErrIntr(), XVphy_Clkout1OBufTdsEnable(), XVphy_GtUserRdyEnable(), XVphy_IBufDsEnable(), XVphy_IntrDisable(), XVphy_IntrEnable(), XVphy_MmcmLockedMaskEnable(), XVphy_MmcmPowerDown(), XVphy_MmcmReset(), XVphy_PowerDownGtPll(), XVphy_ResetGtPll(), XVphy_ResetGtTxRx(), XVphy_SetBufgGtDiv(), XVphy_SetPolarity(), XVphy_SetPrbsSel(), XVphy_SetRxLpm(), XVphy_SetTxPostCursor(), XVphy_SetTxPreEmphasis(), XVphy_SetTxVoltageSwing(), XVphy_TxPrbsForceError(), and XVphy_WriteCfgRefClkSelReg().