 |
vphy
Vitis Drivers API Documentation
|
|
vphy
Vitis Drivers API Documentation
|
This typedef contains configuration information for the Video PHY core. More...
Data Fields | |
| u16 | DeviceId |
| Unique ID of device. More... | |
| UINTPTR | BaseAddr |
| The base address of the core instance. More... | |
| XVphy_GtType | XcvrType |
| VPHY Transceiver Type. More... | |
| u8 | TxChannels |
| No. More... | |
| u8 | RxChannels |
| No. More... | |
| XVphy_ProtocolType | TxProtocol |
| Protocol which TX is used for. More... | |
| XVphy_ProtocolType | RxProtocol |
| Protocol which RX is used for. More... | |
| XVphy_PllRefClkSelType | TxRefClkSel |
| TX REFCLK selection. More... | |
| XVphy_PllRefClkSelType | RxRefClkSel |
| RX REFCLK selection. More... | |
| XVphy_SysClkDataSelType | TxSysPllClkSel |
| TX SYSCLK selection. More... | |
| XVphy_SysClkDataSelType | RxSysPllClkSel |
| RX SYSCLK selectino. More... | |
| u8 | DruIsPresent |
| A data recovery unit (DRU) exists in the design . More... | |
| XVphy_PllRefClkSelType | DruRefClkSel |
| DRU REFCLK selection. More... | |
| XVidC_PixelsPerClock | Ppc |
| Number of input pixels per clock. More... | |
| u8 | TxBufferBypass |
| TX Buffer Bypass is enabled in the design. More... | |
| u8 | HdmiFastSwitch |
| HDMI fast switching is enabled in the design. More... | |
| u8 | TransceiverWidth |
| Transceiver Width seeting in the design. More... | |
| u32 | ErrIrq |
| Error IRQ is enalbed in design. More... | |
| u32 | AxiLiteClkFreq |
| AXI Lite Clock Frequency in Hz. More... | |
| u32 | DrpClkFreq |
| DRP Clock Frequency in Hz. More... | |
| u8 | UseGtAsTxTmdsClk |
| Use 4th GT channel as TX TMDS clock. More... | |
This typedef contains configuration information for the Video PHY core.
| u32 XVphy_Config::AxiLiteClkFreq |
AXI Lite Clock Frequency in Hz.
| UINTPTR XVphy_Config::BaseAddr |
The base address of the core instance.
Referenced by XVphy_CfgErrIntr(), XVphy_CfgInitialize(), XVphy_Clkout1OBufTdsEnable(), XVphy_GetSysClkDataSel(), XVphy_GetSysClkOutSel(), XVphy_GetVersion(), XVphy_GtUserRdyEnable(), XVphy_IBufDsEnable(), XVphy_InterruptHandler(), XVphy_IntrDisable(), XVphy_IntrEnable(), XVphy_IsPllLocked(), XVphy_MmcmLocked(), XVphy_MmcmLockedMaskEnable(), XVphy_MmcmPowerDown(), XVphy_MmcmReset(), XVphy_PowerDownGtPll(), XVphy_RegisterDebug(), XVphy_ResetGtPll(), XVphy_ResetGtTxRx(), XVphy_SelfTest(), XVphy_SetBufgGtDiv(), XVphy_SetPolarity(), XVphy_SetPrbsSel(), XVphy_SetRxLpm(), XVphy_SetTxPostCursor(), XVphy_SetTxPreEmphasis(), XVphy_SetTxVoltageSwing(), XVphy_TxPrbsForceError(), and XVphy_WriteCfgRefClkSelReg().
| u16 XVphy_Config::DeviceId |
Unique ID of device.
| u32 XVphy_Config::DrpClkFreq |
DRP Clock Frequency in Hz.
| u8 XVphy_Config::DruIsPresent |
A data recovery unit (DRU) exists in the design .
Referenced by XVphy_GetRefClkSourcesCount(), and XVphy_IBufDsEnable().
| XVphy_PllRefClkSelType XVphy_Config::DruRefClkSel |
DRU REFCLK selection.
Referenced by XVphy_CfgInitialize(), XVphy_GetRefClkSourcesCount(), and XVphy_IBufDsEnable().
| u32 XVphy_Config::ErrIrq |
Error IRQ is enalbed in design.
| u8 XVphy_Config::HdmiFastSwitch |
HDMI fast switching is enabled in the design.
| XVidC_PixelsPerClock XVphy_Config::Ppc |
Number of input pixels per clock.
| u8 XVphy_Config::RxChannels |
| XVphy_ProtocolType XVphy_Config::RxProtocol |
Protocol which RX is used for.
Referenced by XVphy_DirReconfig(), XVphy_GetRefClkSourcesCount(), XVphy_IsHDMI(), XVphy_MmcmStart(), and XVphy_RegisterDebug().
| XVphy_PllRefClkSelType XVphy_Config::RxRefClkSel |
RX REFCLK selection.
Referenced by XVphy_CfgInitialize(), XVphy_GetRefClkSourcesCount(), and XVphy_IBufDsEnable().
| XVphy_SysClkDataSelType XVphy_Config::RxSysPllClkSel |
RX SYSCLK selectino.
Referenced by XVphy_CfgInitialize().
| u8 XVphy_Config::TransceiverWidth |
Transceiver Width seeting in the design.
| u8 XVphy_Config::TxBufferBypass |
TX Buffer Bypass is enabled in the design.
| u8 XVphy_Config::TxChannels |
| XVphy_ProtocolType XVphy_Config::TxProtocol |
Protocol which TX is used for.
Referenced by XVphy_DirReconfig(), XVphy_GetRefClkSourcesCount(), XVphy_IsHDMI(), XVphy_MmcmStart(), and XVphy_RegisterDebug().
| XVphy_PllRefClkSelType XVphy_Config::TxRefClkSel |
TX REFCLK selection.
Referenced by XVphy_CfgInitialize(), XVphy_GetRefClkSourcesCount(), and XVphy_IBufDsEnable().
| XVphy_SysClkDataSelType XVphy_Config::TxSysPllClkSel |
TX SYSCLK selection.
Referenced by XVphy_CfgInitialize().
| u8 XVphy_Config::UseGtAsTxTmdsClk |
Use 4th GT channel as TX TMDS clock.
Referenced by XVphy_Ch2Ids().
| XVphy_GtType XVphy_Config::XcvrType |
VPHY Transceiver Type.
Referenced by XVphy_CfgInitialize(), XVphy_Ch2Ids(), XVphy_ClkReconfig(), XVphy_DirReconfig(), XVphy_GetPllType(), XVphy_GetSysClkDataSel(), XVphy_GetSysClkOutSel(), XVphy_PllCalculator(), XVphy_PllInitialize(), XVphy_RegisterDebug(), and XVphy_WriteCfgRefClkSelReg().