vphy
Vitis Drivers API Documentation
XVphy_Config Struct Reference

This typedef contains configuration information for the Video PHY core. More...

Data Fields

u16 DeviceId
 Device instance ID. More...
 
UINTPTR BaseAddr
 The base address of the core instance. More...
 
XVphy_GtType XcvrType
 VPHY Transceiver Type. More...
 
u8 TxChannels
 No. More...
 
u8 RxChannels
 No. More...
 
XVphy_ProtocolType TxProtocol
 Protocol which TX is used for. More...
 
XVphy_ProtocolType RxProtocol
 Protocol which RX is used for. More...
 
XVphy_PllRefClkSelType TxRefClkSel
 TX REFCLK selection. More...
 
XVphy_PllRefClkSelType RxRefClkSel
 RX REFCLK selection. More...
 
XVphy_SysClkDataSelType TxSysPllClkSel
 TX SYSCLK selection. More...
 
XVphy_SysClkDataSelType RxSysPllClkSel
 RX SYSCLK selectino. More...
 
u8 DruIsPresent
 A data recovery unit (DRU) exists in the design . More...
 
XVphy_PllRefClkSelType DruRefClkSel
 DRU REFCLK selection. More...
 
XVidC_PixelsPerClock Ppc
 Number of input pixels per clock. More...
 
u8 TxBufferBypass
 TX Buffer Bypass is enabled in the design. More...
 
u8 HdmiFastSwitch
 HDMI fast switching is enabled in the design. More...
 
u8 TransceiverWidth
 Transceiver Width seeting in the design. More...
 
u32 ErrIrq
 Error IRQ is enalbed in design. More...
 
u32 AxiLiteClkFreq
 AXI Lite Clock Frequency in Hz. More...
 
u32 DrpClkFreq
 DRP Clock Frequency in Hz. More...
 
u8 UseGtAsTxTmdsClk
 Use 4th GT channel as TX TMDS clock. More...
 

Detailed Description

This typedef contains configuration information for the Video PHY core.

Field Documentation

u32 XVphy_Config::AxiLiteClkFreq

AXI Lite Clock Frequency in Hz.

u16 XVphy_Config::DeviceId

Device instance ID.

u32 XVphy_Config::DrpClkFreq

DRP Clock Frequency in Hz.

u8 XVphy_Config::DruIsPresent

A data recovery unit (DRU) exists in the design .

Referenced by XVphy_GetRefClkSourcesCount(), and XVphy_IBufDsEnable().

XVphy_PllRefClkSelType XVphy_Config::DruRefClkSel

DRU REFCLK selection.

Referenced by XVphy_CfgInitialize(), XVphy_GetRefClkSourcesCount(), and XVphy_IBufDsEnable().

u32 XVphy_Config::ErrIrq

Error IRQ is enalbed in design.

u8 XVphy_Config::HdmiFastSwitch

HDMI fast switching is enabled in the design.

XVidC_PixelsPerClock XVphy_Config::Ppc

Number of input pixels per clock.

u8 XVphy_Config::RxChannels

No.

of active channels in RX

Referenced by XVphy_Ch2Ids(), and XVphy_RegisterDebug().

XVphy_ProtocolType XVphy_Config::RxProtocol
XVphy_PllRefClkSelType XVphy_Config::RxRefClkSel
XVphy_SysClkDataSelType XVphy_Config::RxSysPllClkSel

RX SYSCLK selectino.

Referenced by XVphy_CfgInitialize().

u8 XVphy_Config::TransceiverWidth

Transceiver Width seeting in the design.

u8 XVphy_Config::TxBufferBypass

TX Buffer Bypass is enabled in the design.

u8 XVphy_Config::TxChannels

No.

of active channels in TX

Referenced by XVphy_Ch2Ids(), and XVphy_RegisterDebug().

XVphy_ProtocolType XVphy_Config::TxProtocol
XVphy_PllRefClkSelType XVphy_Config::TxRefClkSel
XVphy_SysClkDataSelType XVphy_Config::TxSysPllClkSel

TX SYSCLK selection.

Referenced by XVphy_CfgInitialize().

u8 XVphy_Config::UseGtAsTxTmdsClk

Use 4th GT channel as TX TMDS clock.

Referenced by XVphy_Ch2Ids().