![]() |
v_tpg
Vitis Drivers API Documentation
|
#include "xparameters.h"#include "sleep.h"#include "xv_tpg.h"#include "xvtc.h"#include "xvidc.h"Macros | |
| #define | VideoClockGen_WriteReg(RegOffset, Data) Xil_Out32((XPAR_VIDEO_CLK_WIZ_BASEADDR) + (RegOffset), (u32)(Data)) |
| Macro to write to Video Clock Generator register. More... | |
| #define | VideoClockGen_ReadReg(RegOffset) Xil_In32((XPAR_VIDEO_CLK_WIZ_BASEADDR) + (RegOffset)) |
| Macro to read from Video Clock Generator register. More... | |
Functions | |
| int | driverInit () |
| Initialize VTC and TPG driver instances. More... | |
| void | videoIpConfig (XVidC_VideoMode videoMode) |
| Configure video IP cores for specified video mode. More... | |
| int | videoClockConfig (XVidC_VideoMode videoMode) |
| Configure video clock generator for specified video mode. More... | |
| void | resetIp (void) |
| Reset video IP cores. More... | |
| int | main () |
| Main function to test TPG video pipeline. More... | |
| #define VideoClockGen_ReadReg | ( | RegOffset | ) | Xil_In32((XPAR_VIDEO_CLK_WIZ_BASEADDR) + (RegOffset)) |
Macro to read from Video Clock Generator register.
Referenced by videoClockConfig().
| #define VideoClockGen_WriteReg | ( | RegOffset, | |
| Data | |||
| ) | Xil_Out32((XPAR_VIDEO_CLK_WIZ_BASEADDR) + (RegOffset), (u32)(Data)) |
Macro to write to Video Clock Generator register.
Referenced by videoClockConfig().
| int driverInit | ( | ) |
Initialize VTC and TPG driver instances.
This function looks up the configuration for VTC and both TPG instances, then initializes them with their respective base addresses.
References XV_tpg_Config::BaseAddress, XV_tpg_CfgInitialize(), and XV_tpg_LookupConfig().
Referenced by main().
| int main | ( | ) |
Main function to test TPG video pipeline.
This function tests the TPG video pipeline by sequentially running tests for different video modes (1080p60, 4K30, and optionally 4K60). Each test configures the clock, video IPs, and verifies video lock status.
References XV_tpg::Config, driverInit(), XV_tpg_Config::PixPerClk, resetIp(), videoClockConfig(), and videoIpConfig().
| void resetIp | ( | void | ) |
Reset video IP cores.
This function asserts and then releases reset for all HLS-based video IP cores in the system using GPIO control.
Referenced by main().
| int videoClockConfig | ( | XVidC_VideoMode | videoMode | ) |
Configure video clock generator for specified video mode.
This function programs the video clock wizard with appropriate PLL settings to generate the required pixel clock for the specified video mode and pixels-per-clock configuration.
| videoMode | Video mode that determines clock frequency requirements |
References XV_tpg::Config, XV_tpg_Config::PixPerClk, VideoClockGen_ReadReg, and VideoClockGen_WriteReg.
Referenced by main().
| void videoIpConfig | ( | XVidC_VideoMode | videoMode | ) |
Configure video IP cores for specified video mode.
This function configures both TPG instances and VTC with timing parameters for the specified video mode. TPG0 generates color bars, TPG1 is configured for passthrough mode, and VTC generates timing signals.
| videoMode | Video mode to configure (e.g., 1080p60, 4K30, 4K60) |
References XV_tpg_Config::BaseAddress, XV_tpg::Config, XV_tpg_Config::PixPerClk, XTPG_BKGND_COLOR_BARS, XV_TPG_CTRL_ADDR_AP_CTRL, XV_tpg_Set_bckgndId(), XV_tpg_Set_colorFormat(), XV_tpg_Set_enableInput(), XV_tpg_Set_height(), XV_tpg_Set_ovrlayId(), XV_tpg_Set_passthruEndX(), XV_tpg_Set_passthruEndY(), XV_tpg_Set_passthruStartX(), XV_tpg_Set_passthruStartY(), XV_tpg_Set_width(), and XV_tpg_WriteReg.
Referenced by main().