Data Structures
struct	XAxiVdma_Config
	This typedef contains the hardware configuration information for a VDMA device. More...

struct	XAxiVdma_DmaSetup
	The XAxiVdma_DmaSetup structure contains all the necessary information to start a frame write or read. More...

struct	XAxiVdma_FrameCounter
	The XAxiVdmaFrameCounter structure contains the interrupt threshold settings for both the transmit and the receive channel. More...

struct	XAxiVdma_ChannelCallBack
	Channel callback functions. More...

struct	XAxiVdma
	The XAxiVdma driver instance data. More...

Macros
#define	XAXIVDMA_WRITE 1
	VDMA data transfer direction. More...

#define	XAXIVDMA_READ 2
	DMA transfer from memory. More...

#define	XAXIVDMA_CHAN_FSYNC 0
	Frame Sync Source Selection. More...

#define	XAXIVDMA_EXTERNAL_GENLOCK 0
	GenLock Source Selection. More...

#define	XAXIVDMA_GENLOCK_MASTER 0
	GenLock Mode Constants. More...

#define	XAXIVDMA_HANDLER_GENERAL 1
	Interrupt type for setting up callback. More...

#define	XAXIVDMA_HANDLER_ERROR 2
	Error Interrupt Type. More...

#define	XAXIVDMA_DEVICE_READY 0x11111111
	Flag to signal that device is ready to be used. More...

#define	XAXIVDMA_ENABLE_DBG_THRESHOLD_REG 0x01
	Debug Configuration Parameter Constants (C_ENABLE_DEBUG_INFO_*) More...

#define	XAxiVdma_ChannelHiFrmAddrEnable(Channel)
	Set the channel to enable access to higher Frame Buffer Addresses (SG=0) More...

#define	XAxiVdma_ChannelHiFrmAddrDisable(Channel)
	Set the channel to disable access higher Frame Buffer Addresses (SG=0) More...

#define	XAXIVDMA_MISMATCH_ERROR 0x80000010
	Frame/Line Mismatch Error This is a typical DMA Internal Error, which on detection doesnt require a reset (as opposed to other errors). More...

#define	XAxiVdma_ReadReg(BaseAddress, RegOffset) XAxiVdma_In32((BaseAddress) + (RegOffset))
	Read the given register. More...

#define	XAxiVdma_WriteReg(BaseAddress, RegOffset, Data) XAxiVdma_Out32((BaseAddress) + (RegOffset), (Data))
	Write the given register. More...

Typedefs
typedef void(*	XAxiVdma_CallBack )(void *CallBackRef, u32 InterruptTypes)
	Callback type for general interrupts. More...

typedef void(*	XAxiVdma_ErrorCallBack )(void *CallBackRef, u32 ErrorMask)
	Callback type for Error interrupt. More...

Functions
XAxiVdma_Channel *	XAxiVdma_GetChannel (XAxiVdma *InstancePtr, u16 Direction)
	Get a channel. More...

int	XAxiVdma_CfgInitialize (XAxiVdma InstancePtr, XAxiVdma_Config CfgPtr, UINTPTR EffectiveAddr)
	Initialize the driver with hardware configuration. More...

void	XAxiVdma_Reset (XAxiVdma *InstancePtr, u16 Direction)
	This function resets one DMA channel. More...

int	XAxiVdma_ResetNotDone (XAxiVdma *InstancePtr, u16 Direction)
	This function checks one DMA channel for reset completion. More...

int	XAxiVdma_IsBusy (XAxiVdma *InstancePtr, u16 Direction)
	Check whether a DMA channel is busy. More...

u32	XAxiVdma_CurrFrameStore (XAxiVdma *InstancePtr, u16 Direction)
	Get the current frame that hardware is working on. More...

u32	XAxiVdma_GetVersion (XAxiVdma *InstancePtr)
	Get the version of the hardware. More...

u32	XAxiVdma_GetStatus (XAxiVdma *InstancePtr, u16 Direction)
	Get the status of a channel. More...

int	XAxiVdma_SetLineBufThreshold (XAxiVdma *InstancePtr, int LineBufThreshold, u16 Direction)
	Configure Line Buffer Threshold. More...

int	XAxiVdma_FsyncSrcSelect (XAxiVdma *InstancePtr, u32 Source, u16 Direction)
	Configure Frame Sync Source and valid only when C_USE_FSYNC is enabled. More...

int	XAxiVdma_GenLockSourceSelect (XAxiVdma *InstancePtr, u32 Source, u16 Direction)
	Configure Gen Lock Source. More...

int	XAxiVdma_StartParking (XAxiVdma *InstancePtr, int FrameIndex, u16 Direction)
	Start parking mode on a certain frame. More...

void	XAxiVdma_StopParking (XAxiVdma *InstancePtr, u16 Direction)
	Exit parking mode, the channel will return to circular buffer mode. More...

void	XAxiVdma_StartFrmCntEnable (XAxiVdma *InstancePtr, u16 Direction)
	Start frame count enable on one channel. More...

int	XAxiVdma_SetBdAddrs (XAxiVdma *InstancePtr, u32 BdAddrPhys, u32 BdAddrVirt, int NumBds, u16 Direction)
	Set BD addresses to be different. More...

int	XAxiVdma_StartWriteFrame (XAxiVdma InstancePtr, XAxiVdma_DmaSetup DmaConfigPtr)
	Start a write operation. More...

int	XAxiVdma_StartReadFrame (XAxiVdma InstancePtr, XAxiVdma_DmaSetup DmaConfigPtr)
	Start a read operation. More...

int	XAxiVdma_DmaConfig (XAxiVdma InstancePtr, u16 Direction, XAxiVdma_DmaSetup DmaConfigPtr)
	Configure one DMA channel using the configuration structure. More...

int	XAxiVdma_DmaSetBufferAddr (XAxiVdma InstancePtr, u16 Direction, UINTPTR BufferAddrSet)
	Configure buffer addresses for one DMA channel. More...

int	XAxiVdma_DmaStart (XAxiVdma *InstancePtr, u16 Direction)
	Start one DMA channel. More...

void	XAxiVdma_DmaStop (XAxiVdma *InstancePtr, u16 Direction)
	Stop one DMA channel. More...

void	XAxiVdma_DmaRegisterDump (XAxiVdma *InstancePtr, u16 Direction)
	Dump registers of one DMA channel. More...

int	XAxiVdma_SetFrameCounter (XAxiVdma InstancePtr, XAxiVdma_FrameCounter CfgPtr)
	Set the frame counter and delay counter for both channels. More...

void	XAxiVdma_GetFrameCounter (XAxiVdma InstancePtr, XAxiVdma_FrameCounter CfgPtr)
	Get the frame counter and delay counter for both channels. More...

int	XAxiVdma_SetFrmStore (XAxiVdma *InstancePtr, u8 FrmStoreNum, u16 Direction)
	Set the number of frame store buffers to use. More...

void	XAxiVdma_GetFrmStore (XAxiVdma InstancePtr, u8 FrmStoreNum, u16 Direction)
	Get the number of frame store buffers to use. More...

int	XAxiVdma_GetDmaChannelErrors (XAxiVdma *InstancePtr, u16 Direction)
	Check for DMA Channel Errors. More...

int	XAxiVdma_ClearDmaChannelErrors (XAxiVdma *InstancePtr, u16 Direction, u32 ErrorMask)
	Clear DMA Channel Errors. More...

XAxiVdma_Config *	XAxiVdma_LookupConfig (u16 DeviceId)
	Look up the hardware configuration for a device instance. More...

void	XAxiVdma_IntrEnable (XAxiVdma *InstancePtr, u32 IntrType, u16 Direction)
	Enable specific interrupts for a channel. More...

void	XAxiVdma_IntrDisable (XAxiVdma *InstancePtr, u32 IntrType, u16 Direction)
	Disable specific interrupts for a channel. More...

u32	XAxiVdma_IntrGetPending (XAxiVdma *InstancePtr, u16 Direction)
	Get the pending interrupts of a channel. More...

void	XAxiVdma_IntrClear (XAxiVdma *InstancePtr, u32 IntrType, u16 Direction)
	Clear the pending interrupts specified by the bit mask. More...

int	XAxiVdma_MaskS2MMErrIntr (XAxiVdma *InstancePtr, u32 ErrorMask, u16 Direction)
	Masks the S2MM error interrupt for the provided error mask value. More...

void	XAxiVdma_ReadIntrHandler (void *InstancePtr)
	Interrupt handler for the read channel. More...

void	XAxiVdma_WriteIntrHandler (void *InstancePtr)
	Interrupt handler for the write channel. More...

int	XAxiVdma_SetCallBack (XAxiVdma InstancePtr, u32 HandlerType, void CallBackFunc, void *CallBackRef, u16 Direction)
	Set call back function and call back reference pointer for one channel. More...

int	XAxiVdma_Selftest (XAxiVdma *InstancePtr)
	Runs a self-test on the driver/device. More...

void	XAxiVdma_ChannelInit (XAxiVdma_Channel *Channel)
	Initialize a channel of a DMA engine. More...

int	XAxiVdma_ChannelResetNotDone (XAxiVdma_Channel *Channel)
	This function checks whether reset operation is done. More...

void	XAxiVdma_ChannelReset (XAxiVdma_Channel *Channel)
	This function resets one DMA channel. More...

int	XAxiVdma_ChannelIsBusy (XAxiVdma_Channel *Channel)
	Check whether a DMA channel is busy. More...

u32	XAxiVdma_ChannelGetStatus (XAxiVdma_Channel *Channel)
	Get the current status of a channel. More...

int	XAxiVdma_ChannelStartParking (XAxiVdma_Channel *Channel)
	Set the channel to run in parking mode. More...

void	XAxiVdma_ChannelStopParking (XAxiVdma_Channel *Channel)
	Set the channel to run in circular mode, exiting parking mode. More...

void	XAxiVdma_ChannelStartFrmCntEnable (XAxiVdma_Channel *Channel)
	Set the channel to run in frame count enable mode. More...

int	XAxiVdma_ChannelSetBdAddrs (XAxiVdma_Channel *Channel, UINTPTR BdAddrPhys, UINTPTR BdAddrVirt)
	Setup BD addresses to a different memory region. More...

int	XAxiVdma_ChannelStartTransfer (XAxiVdma_Channel Channel, XAxiVdma_ChannelSetup ChannelCfgPtr)
	Start a transfer. More...

int	XAxiVdma_ChannelConfig (XAxiVdma_Channel Channel, XAxiVdma_ChannelSetup ChannelCfgPtr)
	Configure one DMA channel using the configuration structure. More...

int	XAxiVdma_ChannelSetBufferAddr (XAxiVdma_Channel Channel, UINTPTR BufferAddrSet, int NumFrames)
	Configure buffer addresses for one DMA channel. More...

int	XAxiVdma_ChannelStart (XAxiVdma_Channel *Channel)
	Start one DMA channel. More...

void	XAxiVdma_ChannelStop (XAxiVdma_Channel *Channel)
	Stop one DMA channel. More...

void	XAxiVdma_ChannelRegisterDump (XAxiVdma_Channel *Channel)
	Dump registers from one DMA channel. More...

int	XAxiVdma_ChannelSetFrmCnt (XAxiVdma_Channel *Channel, u8 FrmCnt, u8 DlyCnt)
	Set the frame counter and delay counter for one channel. More...

void	XAxiVdma_ChannelGetFrmCnt (XAxiVdma_Channel Channel, u8 FrmCnt, u8 *DlyCnt)
	Get the frame counter and delay counter for both channels. More...

void	XAxiVdma_ChannelEnableIntr (XAxiVdma_Channel *Channel, u32 IntrType)
	Enable interrupts for a channel. More...

void	XAxiVdma_ChannelDisableIntr (XAxiVdma_Channel *Channel, u32 IntrType)
	Disable interrupts for a channel. More...

u32	XAxiVdma_ChannelGetPendingIntr (XAxiVdma_Channel *Channel)
	Get pending interrupts of a channel. More...

void	XAxiVdma_ChannelIntrClear (XAxiVdma_Channel *Channel, u32 IntrType)
	Clear interrupts of a channel. More...

u32	XAxiVdma_ChannelGetEnabledIntr (XAxiVdma_Channel *Channel)
	Get the enabled interrupts of a channel. More...

Variables
u16	XAxiVdma_Config::DeviceId
	DeviceId is the unique ID of the device. More...

UINTPTR	XAxiVdma_Config::BaseAddress
	BaseAddress is the physical base address of the device's registers More...

u16	XAxiVdma_Config::MaxFrameStoreNum
	The maximum number of Frame Stores. More...

int	XAxiVdma_Config::HasMm2S
	Whether hw build has read channel. More...

int	XAxiVdma_Config::HasMm2SDRE
	Read channel supports unaligned transfer. More...

int	XAxiVdma_Config::Mm2SWordLen
	Read channel word length. More...

int	XAxiVdma_Config::HasS2Mm
	Whether hw build has write channel. More...

int	XAxiVdma_Config::HasS2MmDRE
	Write channel supports unaligned transfer. More...

int	XAxiVdma_Config::S2MmWordLen
	Write channel word length. More...

int	XAxiVdma_Config::HasSG
	Whether hardware has SG engine. More...

int	XAxiVdma_Config::EnableVIDParamRead
	Read Enable for video parameters in direct register mode. More...

int	XAxiVdma_Config::UseFsync
	DMA operations synchronized to Frame Sync. More...

int	XAxiVdma_Config::FlushonFsync
	VDMA Transactions are flushed & channel states reset on Frame Sync More...

int	XAxiVdma_Config::Mm2SBufDepth
	Depth of Read Channel Line Buffer FIFO. More...

int	XAxiVdma_Config::S2MmBufDepth
	Depth of Write Channel Line Buffer FIFO. More...

int	XAxiVdma_Config::Mm2SGenLock
	Mm2s Gen Lock Mode. More...

int	XAxiVdma_Config::S2MmGenLock
	S2Mm Gen Lock Mode. More...

int	XAxiVdma_Config::InternalGenLock
	Internal Gen Lock. More...

int	XAxiVdma_Config::S2MmSOF
	S2MM Start of Flag Enable. More...

int	XAxiVdma_Config::Mm2SStreamWidth
	MM2S TData Width. More...

int	XAxiVdma_Config::S2MmStreamWidth
	S2MM TData Width. More...

int	XAxiVdma_Config::Mm2SThresRegEn
	MM2S Threshold Register Enable Flag This corresponds to C_ENABLE_DEBUG_INFO_1 configuration parameter. More...

int	XAxiVdma_Config::Mm2SFrmStoreRegEn
	MM2S Frame Store Register Enable Flag This corresponds to C_ENABLE_DEBUG_INFO_5 configuration parameter. More...

int	XAxiVdma_Config::Mm2SDlyCntrEn
	MM2S Delay Counter (Control Reg) Enable Flag This corresponds to C_ENABLE_DEBUG_INFO_6 configuration parameter. More...

int	XAxiVdma_Config::Mm2SFrmCntrEn
	MM2S Frame Counter (Control Reg) Enable Flag This corresponds to C_ENABLE_DEBUG_INFO_7 configuration parameter. More...

int	XAxiVdma_Config::S2MmThresRegEn
	S2MM Threshold Register Enable Flag This corresponds to C_ENABLE_DEBUG_INFO_9 configuration parameter. More...

int	XAxiVdma_Config::S2MmFrmStoreRegEn
	S2MM Frame Store Register Enable Flag This corresponds to C_ENABLE_DEBUG_INFO_13 configuration parameter. More...

int	XAxiVdma_Config::S2MmDlyCntrEn
	S2MM Delay Counter (Control Reg) Enable Flag This corresponds to C_ENABLE_DEBUG_INFO_14 configuration parameter. More...

int	XAxiVdma_Config::S2MmFrmCntrEn
	S2MM Frame Counter (Control Reg) Enable Flag This corresponds to C_ENABLE_DEBUG_INFO_15 configuration parameter. More...

int	XAxiVdma_Config::EnableAllDbgFeatures
	Enable all Debug features This corresponds to C_ENABLE_DEBUG_ALL configuration parameter. More...

int	XAxiVdma_Config::AddrWidth
	Address Width. More...

u8	XAxiVdma_Config::HasVFlip
	Whether hardware has Vertical Flip enabled(c_enable_vert_flip) More...

UINTPTR	XAxiVdma_Config::IntrParent
	Bits[11:0] Interrupt-id Bits[15:12] trigger type and level flags. More...

int	XAxiVdma_DmaSetup::VertSizeInput
	Vertical size input. More...

int	XAxiVdma_DmaSetup::HoriSizeInput
	Horizontal size input. More...

int	XAxiVdma_DmaSetup::Stride
	Stride. More...

int	XAxiVdma_DmaSetup::FrameDelay
	Frame Delay. More...

int	XAxiVdma_DmaSetup::EnableCircularBuf
	Circular Buffer Mode? More...

int	XAxiVdma_DmaSetup::EnableSync
	Gen-Lock Mode? More...

int	XAxiVdma_DmaSetup::PointNum
	Master we synchronize with. More...

int	XAxiVdma_DmaSetup::EnableFrameCounter
	Frame Counter Enable. More...

UINTPTR	XAxiVdma_DmaSetup::FrameStoreStartAddr [XAXIVDMA_MAX_FRAMESTORE]
	Start Addresses of Frame Store Buffers. More...

int	XAxiVdma_DmaSetup::FixedFrameStoreAddr
	Fixed Frame Store Address index. More...

int	XAxiVdma_DmaSetup::GenLockRepeat
	Gen-Lock Repeat? More...

u8	XAxiVdma_DmaSetup::EnableVFlip
	Vertical Flip state. More...

u8	XAxiVdma_FrameCounter::ReadFrameCount
	Interrupt threshold for Receive. More...

u8	XAxiVdma_FrameCounter::ReadDelayTimerCount
	Delay timer threshold for receive. More...

u8	XAxiVdma_FrameCounter::WriteFrameCount
	Interrupt threshold for transmit. More...

u8	XAxiVdma_FrameCounter::WriteDelayTimerCount
	Delay timer threshold for transmit. More...

XAxiVdma_CallBack	XAxiVdma_ChannelCallBack::CompletionCallBack
	Call back for completion intr. More...

void *	XAxiVdma_ChannelCallBack::CompletionRef
	Call back ref. More...

XAxiVdma_ErrorCallBack	XAxiVdma_ChannelCallBack::ErrCallBack
	Call back for error intr. More...

void *	XAxiVdma_ChannelCallBack::ErrRef
	Call back ref. More...

UINTPTR	XAxiVdma::BaseAddr
	Memory address for this device. More...

int	XAxiVdma::HasSG
	Whether hardware has SG engine. More...

int	XAxiVdma::IsReady
	Whether driver is initialized. More...

int	XAxiVdma::MaxNumFrames
	Number of frames to work on. More...

int	XAxiVdma::HasMm2S
	Whether hw build has read channel. More...

int	XAxiVdma::HasMm2SDRE
	Whether read channel has DRE. More...

int	XAxiVdma::HasS2Mm
	Whether hw build has write channel. More...

int	XAxiVdma::HasS2MmDRE
	Whether write channel has DRE. More...

int	XAxiVdma::EnableVIDParamRead
	Read Enable for video parameters in direct register mode. More...

int	XAxiVdma::UseFsync
	DMA operations synchronized to Frame Sync. More...

int	XAxiVdma::InternalGenLock
	Internal Gen Lock. More...

XAxiVdma_ChannelCallBack	XAxiVdma::ReadCallBack
	Call back for read channel. More...

XAxiVdma_ChannelCallBack	XAxiVdma::WriteCallBack
	Call back for write channel. More...

XAxiVdma_Channel	XAxiVdma::ReadChannel
	Channel to read from memory. More...

XAxiVdma_Channel	XAxiVdma::WriteChannel
	Channel to write to memory. More...

int	XAxiVdma::AddrWidth
	Address Width. More...

Buffer Descriptor Alignment
#define	XAXIVDMA_BD_MINIMUM_ALIGNMENT 0x20
	Minimum byte alignment requirement for descriptors. More...

#define	XAXIVDMA_BD_MINIMUM_ALIGNMENT_WD 0x8
	Minimum word alignment requirement for descriptors. More...

#define	XAXIVDMA_MAX_FRAMESTORE 32
	Maximum number of the frame store. More...

#define	XAXIVDMA_MAX_FRAMESTORE_64 16
	Maximum # of the frame store for 64 bit. More...

Maximum transfer length
This is determined by hardware
#define	XAXIVDMA_MAX_VSIZE 0x1FFF /* Max vertical size, 8K */

#define	XAXIVDMA_MAX_HSIZE 0xFFFF /* Max horizontal size, 64K */

#define	XAXIVDMA_MAX_STRIDE 0xFFFF /* Max stride size, 64K */

#define	XAXIVDMA_FRMDLY_MAX 0xF
	Maximum frame delay. More...

Device registers
Register sets on TX (Read) and RX (Write) channels are identical The version register is shared by both channels
#define	XAXIVDMA_TX_OFFSET 0x00000000
	TX channel registers base. More...

#define	XAXIVDMA_RX_OFFSET 0x00000030
	RX channel registers base. More...

#define	XAXIVDMA_PARKPTR_OFFSET 0x00000028
	Park Pointer Register. More...

#define	XAXIVDMA_VERSION_OFFSET 0x0000002C
	Version register. More...

#define	XAXIVDMA_CR_OFFSET 0x00000000
	Channel control. More...

#define	XAXIVDMA_SR_OFFSET 0x00000004
	Status. More...

#define	XAXIVDMA_CDESC_OFFSET 0x00000008
	Current descriptor pointer. More...

#define	XAXIVDMA_TDESC_OFFSET 0x00000010
	Tail descriptor pointer. More...

#define	XAXIVDMA_HI_FRMBUF_OFFSET 0x00000014
	32 FrameBuf Sel More...

#define	XAXIVDMA_FRMSTORE_OFFSET 0x00000018
	Frame Store. More...

#define	XAXIVDMA_BUFTHRES_OFFSET 0x0000001C
	Line Buffer Thres. More...

#define	XAXIVDMA_MM2S_ADDR_OFFSET 0x00000050
	MM2S channel Addr. More...

#define	XAXIVDMA_S2MM_ADDR_OFFSET 0x000000A0
	S2MM channel Addr. More...

#define	XAXIVDMA_VFLIP_OFFSET 0x000000EC
	Enable Vertical Flip Register. More...

#define	XAXIVDMA_S2MM_DMA_IRQ_MASK_OFFSET 0x0000003C
	S2MM Err IRQ Mask. More...

Start Addresses Register Array for a Channel
Base offset is set in each channel This set of registers are write only, they can be read when C_ENABLE_VIDPRMTR_READS is 1.
#define	XAXIVDMA_VSIZE_OFFSET 0x00000000
	Vertical size. More...

#define	XAXIVDMA_HSIZE_OFFSET 0x00000004
	Horizontal size. More...

#define	XAXIVDMA_STRD_FRMDLY_OFFSET 0x00000008
	Horizontal size. More...

#define	XAXIVDMA_START_ADDR_OFFSET 0x0000000C
	Start of address. More...

#define	XAXIVDMA_START_ADDR_LEN 0x00000004
	Each entry is 4 bytes. More...

#define	XAXIVDMA_START_ADDR_MSB_OFFSET 0x00000010
	Start of address. More...

Bitmasks of the XAXIVDMA_CR_OFFSET register
#define	XAXIVDMA_CR_RUNSTOP_MASK 0x00000001
	Start/stop DMA channel. More...

#define	XAXIVDMA_CR_TAIL_EN_MASK 0x00000002
	Tail ptr enable or Park. More...

#define	XAXIVDMA_CR_RESET_MASK 0x00000004
	Reset channel. More...

#define	XAXIVDMA_CR_SYNC_EN_MASK 0x00000008
	Gen-lock enable. More...

#define	XAXIVDMA_CR_FRMCNT_EN_MASK 0x00000010
	Frame count enable. More...

#define	XAXIVDMA_CR_FSYNC_SRC_MASK 0x00000060
	Fsync Source Select. More...

#define	XAXIVDMA_CR_GENLCK_SRC_MASK 0x00000080
	Genlock Source Select. More...

#define	XAXIVDMA_CR_RD_PTR_MASK 0x00000F00
	Read pointer number. More...

#define	XAXIVDMA_CR_GENLCK_RPT_MASK 0x00008000
	GenLock Repeat. More...

#define	XAXIVDMA_VFLIP_EN_MASK 0x00000001
	Vertical flip enable. More...

#define	XAXIVDMA_CR_RD_PTR_SHIFT 8
	Shift for read pointer number. More...

Bitmasks of the XAXIVDMA_SR_OFFSET register
This register reports status of a DMA channel, including run/stop/idle state, errors, and interrupts
#define	XAXIVDMA_SR_HALTED_MASK 0x00000001
	DMA channel halted. More...

#define	XAXIVDMA_SR_IDLE_MASK 0x00000002
	DMA channel idle. More...

#define	XAXIVDMA_SR_ERR_INTERNAL_MASK 0x00000010
	Datamover internal err. More...

#define	XAXIVDMA_SR_ERR_SLAVE_MASK 0x00000020
	Datamover slave err. More...

#define	XAXIVDMA_SR_ERR_DECODE_MASK 0x00000040
	Datamover decode err. More...

#define	XAXIVDMA_SR_ERR_FSZ_LESS_MASK 0x00000080
	FSize Less Mismatch err. More...

#define	XAXIVDMA_SR_ERR_LSZ_LESS_MASK 0x00000100
	LSize Less Mismatch err. More...

#define	XAXIVDMA_SR_ERR_SG_SLV_MASK 0x00000200
	SG slave err. More...

#define	XAXIVDMA_SR_ERR_SG_DEC_MASK 0x00000400
	SG decode err. More...

#define	XAXIVDMA_SR_ERR_FSZ_MORE_MASK 0x00000800
	FSize More Mismatch err. More...

#define	XAXIVDMA_SR_ERR_ALL_MASK 0x00000FF0
	All errors. More...

Bitmask for interrupts
These masks are shared by the XAXIVDMA_CR_OFFSET register and the XAXIVDMA_SR_OFFSET register
#define	XAXIVDMA_IXR_FRMCNT_MASK 0x00001000
	Frame count intr. More...

#define	XAXIVDMA_IXR_DELAYCNT_MASK 0x00002000
	Delay interrupt. More...

#define	XAXIVDMA_IXR_ERROR_MASK 0x00004000
	Error interrupt. More...

#define	XAXIVDMA_IXR_COMPLETION_MASK 0x00003000
	Completion interrupts. More...

#define	XAXIVDMA_IXR_ALL_MASK 0x00007000
	All interrupts. More...

Bitmask and shift for delay and coalesce
These masks are shared by the XAXIVDMA_CR_OFFSET register and the XAXIVDMA_SR_OFFSET register
#define	XAXIVDMA_DELAY_MASK 0xFF000000
	Delay timeout counter. More...

#define	XAXIVDMA_FRMCNT_MASK 0x00FF0000
	Frame counter. More...

#define	XAXIVDMA_REGINDEX_MASK 0x00000001
	Register Index. More...

#define	XAXIVDMA_DELAY_SHIFT 24

#define	XAXIVDMA_FRMCNT_SHIFT 16

Bitmask for the XAXIVDMA_CDESC_OFFSET register
#define	XAXIVDMA_CDESC_CURBD_MASK 0xFFFFFFE0
	BD now working on. More...

Bitmask for XAXIVDMA_TDESC_OFFSET register
#define	XAXIVDMA_TDESC_CURBD_MASK 0xFFFFFFE0
	BD to stop on. More...

Bitmask for XAXIVDMA_FRMSTORE_OFFSET register
#define	XAXIVDMA_FRMSTORE_MASK 0x0000003F

Bitmask for XAXIVDMA_PARKPTR_OFFSET register
#define	XAXIVDMA_PARKPTR_READREF_MASK 0x0000001F
	Read frame to park on. More...

#define	XAXIVDMA_PARKPTR_WRTREF_MASK 0x00001F00
	Write frame to park on. More...

#define	XAXIVDMA_PARKPTR_READSTR_MASK 0x001F0000
	Current read frame. More...

#define	XAXIVDMA_PARKPTR_WRTSTR_MASK 0x1F000000
	Current write frame. More...

#define	XAXIVDMA_READREF_SHIFT 0

#define	XAXIVDMA_WRTREF_SHIFT 8

#define	XAXIVDMA_READSTR_SHIFT 16

#define	XAXIVDMA_WRTSTR_SHIFT 24

#define	XAXIVDMA_FRM_MAX 0xF
	At most 16 frames. More...

Bitmask for XAXIVDMA_VERSION_OFFSET register
#define	XAXIVDMA_VERSION_MAJOR_MASK 0xF0000000
	Major version. More...

#define	XAXIVDMA_VERSION_MINOR_MASK 0x0FF00000
	Minor version. More...

#define	XAXIVDMA_VERSION_REV_MASK 0x000F0000
	Revision letter. More...

#define	XAXIVDMA_VERSION_MAJOR_SHIFT 28

#define	XAXIVDMA_VERSION_MINOR_SHIFT 20

Bitmask for XAXIVDMA_S2MM_IRQ_MASK_OFFSET register
#define	XAXIVDMA_S2MM_IRQ_FSZLESS_SOF_ERLY_MASK 0x00000001
	Masks S2MM IRQ FSize Less/SOF Early Error. More...

#define	XAXIVDMA_S2MM_IRQ_LSZLESS_EOL_ERLY_MASK 0x00000002
	Masks S2MM IRQ LSize Less/EOL Early Error. More...

#define	XAXIVDMA_S2MM_IRQ_FSZMORE_SOF_LATE_MASK 0x00000004
	Masks S2MM IRQ FSize More/SOF Late Error. More...

#define	XAXIVDMA_S2MM_IRQ_LSZMORE_EOL_LATE_MASK 0x00000008
	Masks S2MM IRQ LSize More/EOL Late Error. More...

#define	XAXIVDMA_S2MM_IRQ_ERR_ALL_MASK 0x0000000F
	Masks all S2MM IRQ Errors. More...

Frame Delay shared by start address registers and BDs
#define	XAXIVDMA_VSIZE_MASK 0x00001FFF
	Vertical size. More...

#define	XAXIVDMA_HSIZE_MASK 0x0000FFFF
	Horizontal size. More...

#define	XAXIVDMA_STRIDE_MASK 0x0000FFFF
	Stride size. More...

#define	XAXIVDMA_FRMDLY_MASK 0x0F000000
	Frame delay. More...

#define	XAXIVDMA_FRMDLY_SHIFT 24
	Shift for frame delay. More...

Buffer Descriptor offsets
#define	XAXIVDMA_BD_NDESC_OFFSET 0x00
	Next descriptor pointer. More...

#define	XAXIVDMA_BD_START_ADDR_OFFSET 0x08
	Start address. More...

#define	XAXIVDMA_BD_VSIZE_OFFSET 0x10
	Vertical size. More...

#define	XAXIVDMA_BD_HSIZE_OFFSET 0x14
	Horizontal size. More...

#define	XAXIVDMA_BD_STRIDE_OFFSET 0x18
	Stride size. More...

#define	XAXIVDMA_BD_NUM_WORDS 7
	Total number of words for one BD. More...

#define	XAXIVDMA_BD_HW_NUM_BYTES 28
	Number of bytes hw used. More...

#define	XAXIVDMA_BD_BYTES_TO_CLEAR 20
	Skip next ptr when clearing. More...

Macro Definition Documentation

#define XAXIVDMA_BD_BYTES_TO_CLEAR 20

Skip next ptr when clearing.

#define XAXIVDMA_BD_HSIZE_OFFSET 0x14

Horizontal size.

#define XAXIVDMA_BD_HW_NUM_BYTES 28

Number of bytes hw used.

#define XAXIVDMA_BD_MINIMUM_ALIGNMENT 0x20

Minimum byte alignment requirement for descriptors.

Referenced by XAxiVdma_SetBdAddrs().

#define XAXIVDMA_BD_MINIMUM_ALIGNMENT_WD 0x8

Minimum word alignment requirement for descriptors.

#define XAXIVDMA_BD_NDESC_OFFSET 0x00

Next descriptor pointer.

#define XAXIVDMA_BD_NUM_WORDS 7

Total number of words for one BD.

#define XAXIVDMA_BD_START_ADDR_OFFSET 0x08

Start address.

#define XAXIVDMA_BD_STRIDE_OFFSET 0x18

Stride size.

#define XAXIVDMA_BD_VSIZE_OFFSET 0x10

Vertical size.

#define XAXIVDMA_BUFTHRES_OFFSET 0x0000001C

Line Buffer Thres.

Referenced by XAxiVdma_CfgInitialize(), and XAxiVdma_SetLineBufThreshold().

#define XAXIVDMA_CDESC_CURBD_MASK 0xFFFFFFE0

BD now working on.

#define XAXIVDMA_CDESC_OFFSET 0x00000008

Current descriptor pointer.

Referenced by XAxiVdma_ChannelRegisterDump(), and XAxiVdma_ChannelStart().

#define XAXIVDMA_CHAN_FSYNC 0

Frame Sync Source Selection.

Referenced by XAxiVdma_FsyncSrcSelect().

#define XAxiVdma_ChannelHiFrmAddrDisable ( Channel )

Value:

{ \
		XAxiVdma_WriteReg(Channel->ChanBase, \
                                  XAXIVDMA_HI_FRMBUF_OFFSET, (XAXIVDMA_REGINDEX_MASK >> 1)); \
        }

Set the channel to disable access higher Frame Buffer Addresses (SG=0)

Parameters

Channel is the pointer to the channel to work on

Referenced by XAxiVdma_ChannelSetBufferAddr().

#define XAxiVdma_ChannelHiFrmAddrEnable ( Channel )

Value:

{ \
		XAxiVdma_WriteReg(Channel->ChanBase, \
                                  XAXIVDMA_HI_FRMBUF_OFFSET, XAXIVDMA_REGINDEX_MASK); \
        }

Set the channel to enable access to higher Frame Buffer Addresses (SG=0)

Parameters

Channel is the pointer to the channel to work on

Referenced by XAxiVdma_ChannelSetBufferAddr().

#define XAXIVDMA_CR_FRMCNT_EN_MASK 0x00000010

Frame count enable.

Referenced by XAxiVdma_ChannelConfig(), and XAxiVdma_ChannelStartFrmCntEnable().

#define XAXIVDMA_CR_FSYNC_SRC_MASK 0x00000060

Fsync Source Select.

Referenced by XAxiVdma_FsyncSrcSelect().

#define XAXIVDMA_CR_GENLCK_RPT_MASK 0x00008000

GenLock Repeat.

Referenced by XAxiVdma_ChannelConfig().

#define XAXIVDMA_CR_GENLCK_SRC_MASK 0x00000080

Genlock Source Select.

Referenced by XAxiVdma_GenLockSourceSelect().

#define XAXIVDMA_CR_OFFSET 0x00000000

Channel control.

Referenced by XAxiVdma_ChannelConfig(), XAxiVdma_ChannelDisableIntr(), XAxiVdma_ChannelEnableIntr(), XAxiVdma_ChannelGetEnabledIntr(), XAxiVdma_ChannelGetFrmCnt(), XAxiVdma_ChannelRegisterDump(), XAxiVdma_ChannelReset(), XAxiVdma_ChannelResetNotDone(), XAxiVdma_ChannelSetFrmCnt(), XAxiVdma_ChannelStart(), XAxiVdma_ChannelStartFrmCntEnable(), XAxiVdma_ChannelStartParking(), XAxiVdma_ChannelStop(), XAxiVdma_ChannelStopParking(), XAxiVdma_FsyncSrcSelect(), and XAxiVdma_GenLockSourceSelect().

#define XAXIVDMA_CR_RD_PTR_MASK 0x00000F00

Read pointer number.

Referenced by XAxiVdma_ChannelConfig().

#define XAXIVDMA_CR_RD_PTR_SHIFT 8

Shift for read pointer number.

Referenced by XAxiVdma_ChannelConfig().

#define XAXIVDMA_CR_RESET_MASK 0x00000004

Reset channel.

Referenced by XAxiVdma_ChannelReset(), and XAxiVdma_ChannelResetNotDone().

#define XAXIVDMA_CR_RUNSTOP_MASK 0x00000001

Start/stop DMA channel.

Referenced by XAxiVdma_ChannelStart(), and XAxiVdma_ChannelStop().

#define XAXIVDMA_CR_SYNC_EN_MASK 0x00000008

Gen-lock enable.

Referenced by XAxiVdma_ChannelConfig().

#define XAXIVDMA_CR_TAIL_EN_MASK 0x00000002

Tail ptr enable or Park.

Referenced by XAxiVdma_ChannelConfig(), XAxiVdma_ChannelStartParking(), and XAxiVdma_ChannelStopParking().

#define XAXIVDMA_DELAY_MASK 0xFF000000

Delay timeout counter.

Referenced by XAxiVdma_ChannelGetFrmCnt(), and XAxiVdma_ChannelSetFrmCnt().

#define XAXIVDMA_DEVICE_READY 0x11111111

Flag to signal that device is ready to be used.

Referenced by XAxiVdma_CfgInitialize(), XAxiVdma_GetFrameCounter(), XAxiVdma_SetCallBack(), and XAxiVdma_SetFrameCounter().

#define XAXIVDMA_ENABLE_DBG_THRESHOLD_REG 0x01

Debug Configuration Parameter Constants (C_ENABLE_DEBUG_INFO_*)

Referenced by XAxiVdma_CfgInitialize(), and XAxiVdma_SetLineBufThreshold().

#define XAXIVDMA_EXTERNAL_GENLOCK 0

GenLock Source Selection.

Referenced by XAxiVdma_GenLockSourceSelect().

#define XAXIVDMA_FRM_MAX 0xF

At most 16 frames.

Referenced by XAxiVdma_ChannelConfig(), and XAxiVdma_StartParking().

#define XAXIVDMA_FRMCNT_MASK 0x00FF0000

Frame counter.

Referenced by XAxiVdma_ChannelGetFrmCnt(), and XAxiVdma_ChannelSetFrmCnt().

#define XAXIVDMA_FRMDLY_MASK 0x0F000000

Frame delay.

#define XAXIVDMA_FRMDLY_MAX 0xF

Maximum frame delay.

Referenced by XAxiVdma_ChannelConfig().

#define XAXIVDMA_FRMDLY_SHIFT 24

Shift for frame delay.

Referenced by XAxiVdma_ChannelConfig().

#define XAXIVDMA_FRMSTORE_OFFSET 0x00000018

Frame Store.

Referenced by XAxiVdma_GetFrmStore(), and XAxiVdma_SetFrmStore().

#define XAXIVDMA_GENLOCK_MASTER 0

GenLock Mode Constants.

Referenced by XAxiVdma_ChannelConfig(), and XAxiVdma_GenLockSourceSelect().

#define XAXIVDMA_HANDLER_ERROR 2

Error Interrupt Type.

Referenced by main(), and XAxiVdma_SetCallBack().

#define XAXIVDMA_HANDLER_GENERAL 1

Interrupt type for setting up callback.

Non-Error Interrupt Type

Referenced by main(), and XAxiVdma_SetCallBack().

#define XAXIVDMA_HI_FRMBUF_OFFSET 0x00000014

32 FrameBuf Sel

#define XAXIVDMA_HSIZE_MASK 0x0000FFFF

Horizontal size.

#define XAXIVDMA_HSIZE_OFFSET 0x00000004

Horizontal size.

Referenced by XAxiVdma_ChannelConfig().

#define XAXIVDMA_IXR_ALL_MASK 0x00007000

All interrupts.

Referenced by main(), XAxiVdma_ChannelDisableIntr(), XAxiVdma_ChannelEnableIntr(), XAxiVdma_ChannelGetEnabledIntr(), XAxiVdma_ChannelGetPendingIntr(), and XAxiVdma_ChannelIntrClear().

#define XAXIVDMA_IXR_COMPLETION_MASK 0x00003000

Completion interrupts.

Referenced by XAxiVdma_ReadIntrHandler(), and XAxiVdma_WriteIntrHandler().

#define XAXIVDMA_IXR_DELAYCNT_MASK 0x00002000

Delay interrupt.

#define XAXIVDMA_IXR_ERROR_MASK 0x00004000

Error interrupt.

Referenced by run_triple_frame_buffer(), XAxiVdma_ReadIntrHandler(), and XAxiVdma_WriteIntrHandler().

#define XAXIVDMA_IXR_FRMCNT_MASK 0x00001000

Frame count intr.

Referenced by run_triple_frame_buffer().

#define XAXIVDMA_MAX_FRAMESTORE 32

Maximum number of the frame store.

Maximum # of the frame store

Referenced by XAxiVdma_ChannelSetBufferAddr().

#define XAXIVDMA_MAX_FRAMESTORE_64 16

Maximum # of the frame store for 64 bit.

Referenced by XAxiVdma_ChannelSetBufferAddr().

#define XAXIVDMA_MISMATCH_ERROR 0x80000010

Frame/Line Mismatch Error This is a typical DMA Internal Error, which on detection doesnt require a reset (as opposed to other errors).

So a MSB bit is set to identify it, from other DMA Internal Errors.

#define XAXIVDMA_MM2S_ADDR_OFFSET 0x00000050

MM2S channel Addr.

Referenced by XAxiVdma_CfgInitialize().

#define XAXIVDMA_PARKPTR_OFFSET 0x00000028

Park Pointer Register.

Referenced by XAxiVdma_ChannelConfig(), XAxiVdma_CurrFrameStore(), and XAxiVdma_StartParking().

#define XAXIVDMA_PARKPTR_READREF_MASK 0x0000001F

Read frame to park on.

Referenced by XAxiVdma_ChannelConfig(), and XAxiVdma_StartParking().

#define XAXIVDMA_PARKPTR_READSTR_MASK 0x001F0000

Current read frame.

Referenced by XAxiVdma_CurrFrameStore().

#define XAXIVDMA_PARKPTR_WRTREF_MASK 0x00001F00

Write frame to park on.

Referenced by XAxiVdma_ChannelConfig(), and XAxiVdma_StartParking().

#define XAXIVDMA_PARKPTR_WRTSTR_MASK 0x1F000000

Current write frame.

Referenced by XAxiVdma_CurrFrameStore().

#define XAXIVDMA_READ 2

DMA transfer from memory.

Referenced by main(), run_triple_frame_buffer(), XAxiVdma_CfgInitialize(), XAxiVdma_CurrFrameStore(), XAxiVdma_GenLockSourceSelect(), XAxiVdma_GetChannel(), XAxiVdma_GetFrameCounter(), XAxiVdma_ReadIntrHandler(), XAxiVdma_Selftest(), XAxiVdma_SetCallBack(), XAxiVdma_SetFrameCounter(), XAxiVdma_StartParking(), and XAxiVdma_StartReadFrame().

#define XAxiVdma_ReadReg	(	BaseAddress,
		RegOffset
	)	XAxiVdma_In32((BaseAddress) + (RegOffset))

Read the given register.

Parameters

BaseAddress	is the base address of the device
RegOffset	is the register offset to be read

Returns: The 32-bit value of the register

Note: C-style signature: u32 XAxiVdma_ReadReg(u32 BaseAddress, u32 RegOffset)

#define XAXIVDMA_REGINDEX_MASK 0x00000001

Register Index.

#define XAXIVDMA_RX_OFFSET 0x00000030

RX channel registers base.

Referenced by XAxiVdma_CfgInitialize(), and XAxiVdma_Selftest().

#define XAXIVDMA_S2MM_ADDR_OFFSET 0x000000A0

S2MM channel Addr.

Referenced by XAxiVdma_CfgInitialize().

#define XAXIVDMA_S2MM_DMA_IRQ_MASK_OFFSET 0x0000003C

S2MM Err IRQ Mask.

Referenced by XAxiVdma_MaskS2MMErrIntr().

#define XAXIVDMA_S2MM_IRQ_ERR_ALL_MASK 0x0000000F

Masks all S2MM IRQ Errors.

Referenced by XAxiVdma_MaskS2MMErrIntr().

#define XAXIVDMA_S2MM_IRQ_FSZLESS_SOF_ERLY_MASK 0x00000001

Masks S2MM IRQ FSize Less/SOF Early Error.

#define XAXIVDMA_S2MM_IRQ_FSZMORE_SOF_LATE_MASK 0x00000004

Masks S2MM IRQ FSize More/SOF Late Error.

#define XAXIVDMA_S2MM_IRQ_LSZLESS_EOL_ERLY_MASK 0x00000002

Masks S2MM IRQ LSize Less/EOL Early Error.

#define XAXIVDMA_S2MM_IRQ_LSZMORE_EOL_LATE_MASK 0x00000008

Masks S2MM IRQ LSize More/EOL Late Error.

#define XAXIVDMA_SR_ERR_ALL_MASK 0x00000FF0

All errors.

#define XAXIVDMA_SR_ERR_DECODE_MASK 0x00000040

Datamover decode err.

#define XAXIVDMA_SR_ERR_FSZ_LESS_MASK 0x00000080

FSize Less Mismatch err.

#define XAXIVDMA_SR_ERR_FSZ_MORE_MASK 0x00000800

FSize More Mismatch err.

#define XAXIVDMA_SR_ERR_INTERNAL_MASK 0x00000010

Datamover internal err.

#define XAXIVDMA_SR_ERR_LSZ_LESS_MASK 0x00000100

LSize Less Mismatch err.

#define XAXIVDMA_SR_ERR_SG_DEC_MASK 0x00000400

SG decode err.

#define XAXIVDMA_SR_ERR_SG_SLV_MASK 0x00000200

SG slave err.

#define XAXIVDMA_SR_ERR_SLAVE_MASK 0x00000020

Datamover slave err.

#define XAXIVDMA_SR_HALTED_MASK 0x00000001

DMA channel halted.

Referenced by XAxiVdma_ChannelIsBusy().

#define XAXIVDMA_SR_IDLE_MASK 0x00000002

DMA channel idle.

Referenced by XAxiVdma_ChannelIsBusy().

#define XAXIVDMA_SR_OFFSET 0x00000004

Status.

Referenced by XAxiVdma_ChannelGetPendingIntr(), XAxiVdma_ChannelGetStatus(), XAxiVdma_ChannelIntrClear(), XAxiVdma_ChannelIsBusy(), and XAxiVdma_ChannelRegisterDump().

#define XAXIVDMA_START_ADDR_LEN 0x00000004

Each entry is 4 bytes.

Referenced by XAxiVdma_ChannelSetBufferAddr().

#define XAXIVDMA_START_ADDR_MSB_OFFSET 0x00000010

Start of address.

Referenced by XAxiVdma_ChannelSetBufferAddr().

#define XAXIVDMA_START_ADDR_OFFSET 0x0000000C

Start of address.

Referenced by XAxiVdma_ChannelSetBufferAddr().

#define XAXIVDMA_STRD_FRMDLY_OFFSET 0x00000008

Horizontal size.

Referenced by XAxiVdma_ChannelConfig().

#define XAXIVDMA_STRIDE_MASK 0x0000FFFF

Stride size.

#define XAXIVDMA_TDESC_CURBD_MASK 0xFFFFFFE0

BD to stop on.

#define XAXIVDMA_TDESC_OFFSET 0x00000010

Tail descriptor pointer.

Referenced by XAxiVdma_ChannelRegisterDump(), and XAxiVdma_ChannelStart().

#define XAXIVDMA_TX_OFFSET 0x00000000

TX channel registers base.

Referenced by XAxiVdma_CfgInitialize(), and XAxiVdma_Selftest().

#define XAXIVDMA_VERSION_MAJOR_MASK 0xF0000000

Major version.

#define XAXIVDMA_VERSION_MINOR_MASK 0x0FF00000

Minor version.

#define XAXIVDMA_VERSION_OFFSET 0x0000002C

Version register.

Referenced by XAxiVdma_GetVersion().

#define XAXIVDMA_VERSION_REV_MASK 0x000F0000

Revision letter.

#define XAXIVDMA_VFLIP_EN_MASK 0x00000001

Vertical flip enable.

Referenced by XAxiVdma_ChannelConfig().

#define XAXIVDMA_VFLIP_OFFSET 0x000000EC

Enable Vertical Flip Register.

Referenced by XAxiVdma_ChannelConfig().

#define XAXIVDMA_VSIZE_MASK 0x00001FFF

Vertical size.

#define XAXIVDMA_VSIZE_OFFSET 0x00000000

Vertical size.

Referenced by XAxiVdma_ChannelStart().

#define XAXIVDMA_WRITE 1

VDMA data transfer direction.

DMA transfer into memory

Referenced by main(), run_triple_frame_buffer(), XAxiVdma_CfgInitialize(), XAxiVdma_ChannelConfig(), XAxiVdma_CurrFrameStore(), XAxiVdma_FsyncSrcSelect(), XAxiVdma_GenLockSourceSelect(), XAxiVdma_GetChannel(), XAxiVdma_GetFrameCounter(), XAxiVdma_MaskS2MMErrIntr(), XAxiVdma_Selftest(), XAxiVdma_SetFrameCounter(), XAxiVdma_StartParking(), XAxiVdma_StartWriteFrame(), and XAxiVdma_WriteIntrHandler().

#define XAxiVdma_WriteReg	(	BaseAddress,
		RegOffset,
		Data
	)	XAxiVdma_Out32((BaseAddress) + (RegOffset), (Data))

Write the given register.

Parameters

BaseAddress	is the base address of the device
RegOffset	is the register offset to be written
Data	is the 32-bit value to write to the register

Returns: None.

Note: C-style signature: void XAxiVdma_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)

Referenced by XAxiVdma_ChannelConfig(), XAxiVdma_ChannelDisableIntr(), XAxiVdma_ChannelEnableIntr(), XAxiVdma_ChannelIntrClear(), XAxiVdma_ChannelReset(), XAxiVdma_ChannelSetBufferAddr(), XAxiVdma_ChannelSetFrmCnt(), XAxiVdma_ChannelStart(), XAxiVdma_ChannelStartFrmCntEnable(), XAxiVdma_ChannelStartParking(), XAxiVdma_ChannelStop(), XAxiVdma_ChannelStopParking(), XAxiVdma_FsyncSrcSelect(), XAxiVdma_GenLockSourceSelect(), XAxiVdma_MaskS2MMErrIntr(), XAxiVdma_SetFrmStore(), XAxiVdma_SetLineBufThreshold(), and XAxiVdma_StartParking().

Typedef Documentation

typedef void(* XAxiVdma_CallBack)(void *CallBackRef, u32 InterruptTypes)

Callback type for general interrupts.

Parameters

CallBackRef	is a callback reference passed in by the upper layer when setting the callback functions, and passed back to the upper layer when the callback is called.
InterruptTypes	indicates the detailed type(s) of the interrupt. Its value equals 'OR'ing one or more XAXIVDMA_IXR_* values defined in xaxivdma_hw.h

typedef void(* XAxiVdma_ErrorCallBack)(void *CallBackRef, u32 ErrorMask)

Callback type for Error interrupt.

Parameters

CallBackRef	is a callback reference passed in by the upper layer when setting the callback function, and it is passed back to the upper layer when the callback is called.
ErrorMask	is a bit mask indicating the cause of the error. Its value equals 'OR'ing one or more XAXIVDMA_IXR_* values defined in xaxivdma_hw.h

Function Documentation

int XAxiVdma_CfgInitialize	(	XAxiVdma *	InstancePtr,
		XAxiVdma_Config *	CfgPtr,
		UINTPTR	EffectiveAddr
	)

Initialize the driver with hardware configuration.

Parameters

InstancePtr	is the pointer to the DMA engine to work on
CfgPtr	is the pointer to the hardware configuration structure
EffectiveAddr	is the virtual address map for the device

Returns

XST_SUCCESS if everything goes fine
XST_FAILURE if reset the hardware failed, need system reset to recover

Note: If channel fails reset, then it will be set as invalid

Referenced by AxiVDMASelfTestExample(), main(), and run_triple_frame_buffer().

int XAxiVdma_ChannelConfig	(	XAxiVdma_Channel *	Channel,
		XAxiVdma_ChannelSetup *	ChannelCfgPtr
	)

Configure one DMA channel using the configuration structure.

Setup the control register and BDs, however, BD addresses are not set.

Parameters

Channel	is the pointer to the channel to work on
ChannelCfgPtr	is the pointer to the setup structure

Returns

XST_SUCCESS if successful
XST_FAILURE if channel has not being initialized
XST_DEVICE_BUSY if the DMA channel is not idle
XST_INVALID_PARAM if fields in ChannelCfgPtr is not valid

References XAxiVdma_ChannelIsBusy(), XAXIVDMA_CR_FRMCNT_EN_MASK, XAXIVDMA_CR_GENLCK_RPT_MASK, XAXIVDMA_CR_OFFSET, XAXIVDMA_CR_RD_PTR_MASK, XAXIVDMA_CR_RD_PTR_SHIFT, XAXIVDMA_CR_SYNC_EN_MASK, XAXIVDMA_CR_TAIL_EN_MASK, XAXIVDMA_FRM_MAX, XAXIVDMA_FRMDLY_MAX, XAXIVDMA_FRMDLY_SHIFT, XAXIVDMA_GENLOCK_MASTER, XAXIVDMA_HSIZE_OFFSET, XAXIVDMA_PARKPTR_OFFSET, XAXIVDMA_PARKPTR_READREF_MASK, XAXIVDMA_PARKPTR_WRTREF_MASK, XAxiVdma_ReadReg, XAXIVDMA_STRD_FRMDLY_OFFSET, XAXIVDMA_VFLIP_EN_MASK, XAXIVDMA_VFLIP_OFFSET, XAXIVDMA_WRITE, and XAxiVdma_WriteReg.

Referenced by XAxiVdma_ChannelStartTransfer(), and XAxiVdma_DmaConfig().

void XAxiVdma_ChannelDisableIntr	(	XAxiVdma_Channel *	Channel,
		u32	IntrType
	)

Disable interrupts for a channel.

Interrupts that are not specified by the interrupt mask are not affected.

Parameters

Channel	is the pointer to the channel to work on
IntrType	is the interrupt mask for interrupts to be disabled

Returns: None.

References XAXIVDMA_CR_OFFSET, XAXIVDMA_IXR_ALL_MASK, XAxiVdma_ReadReg, and XAxiVdma_WriteReg.

Referenced by XAxiVdma_IntrDisable().

void XAxiVdma_ChannelEnableIntr	(	XAxiVdma_Channel *	Channel,
		u32	IntrType
	)

Enable interrupts for a channel.

Interrupts that are not specified by the interrupt mask are not affected.

Parameters

Channel	is the pointer to the channel to work on
IntrType	is the interrupt mask for interrupts to be enabled

Returns: None.

References XAXIVDMA_CR_OFFSET, XAXIVDMA_IXR_ALL_MASK, XAxiVdma_ReadReg, and XAxiVdma_WriteReg.

Referenced by XAxiVdma_IntrEnable().

u32 XAxiVdma_ChannelGetEnabledIntr ( XAxiVdma_Channel * Channel )

Get the enabled interrupts of a channel.

Parameters

Channel is the pointer to the channel to work on

Returns: The interrupts mask represents pending interrupts.

References XAXIVDMA_CR_OFFSET, XAXIVDMA_IXR_ALL_MASK, and XAxiVdma_ReadReg.

Referenced by XAxiVdma_ReadIntrHandler(), and XAxiVdma_WriteIntrHandler().

void XAxiVdma_ChannelGetFrmCnt	(	XAxiVdma_Channel *	Channel,
		u8 *	FrmCnt,
		u8 *	DlyCnt
	)

Get the frame counter and delay counter for both channels.

Parameters

Channel	is the pointer to the channel to work on
FrmCnt	is the pointer for the returning frame counter value
DlyCnt	is the pointer for the returning delay counter value

Returns: None

Note: If FrmCnt return as 0, then the channel is not initialized

References XAXIVDMA_CR_OFFSET, XAXIVDMA_DELAY_MASK, XAXIVDMA_FRMCNT_MASK, and XAxiVdma_ReadReg.

Referenced by XAxiVdma_GetFrameCounter().

u32 XAxiVdma_ChannelGetPendingIntr ( XAxiVdma_Channel * Channel )

Get pending interrupts of a channel.

Parameters

Channel is the pointer to the channel to work on

Returns: The interrupts mask represents pending interrupts.

References XAXIVDMA_IXR_ALL_MASK, XAxiVdma_ReadReg, and XAXIVDMA_SR_OFFSET.

Referenced by XAxiVdma_IntrGetPending(), XAxiVdma_ReadIntrHandler(), and XAxiVdma_WriteIntrHandler().

u32 XAxiVdma_ChannelGetStatus ( XAxiVdma_Channel * Channel )

Get the current status of a channel.

Parameters

Channel is the pointer to the channel to work on

Returns: The status of the channel

References XAxiVdma_ReadReg, and XAXIVDMA_SR_OFFSET.

Referenced by XAxiVdma_CfgInitialize(), and XAxiVdma_GetStatus().

void XAxiVdma_ChannelInit ( XAxiVdma_Channel * Channel )

Initialize a channel of a DMA engine.

This function initializes the BD ring for this channel

Parameters

Channel is the pointer to the DMA channel to work on

Returns: None

Referenced by XAxiVdma_CfgInitialize(), and XAxiVdma_SetFrmStore().

void XAxiVdma_ChannelIntrClear	(	XAxiVdma_Channel *	Channel,
		u32	IntrType
	)

Clear interrupts of a channel.

Interrupts that are not specified by the interrupt mask are not affected.

Parameters

Channel	is the pointer to the channel to work on
IntrType	is the interrupt mask for interrupts to be cleared

Returns: None.

References XAXIVDMA_IXR_ALL_MASK, XAXIVDMA_SR_OFFSET, and XAxiVdma_WriteReg.

Referenced by XAxiVdma_IntrClear(), XAxiVdma_ReadIntrHandler(), and XAxiVdma_WriteIntrHandler().

int XAxiVdma_ChannelIsBusy ( XAxiVdma_Channel * Channel )

Check whether a DMA channel is busy.

Parameters

Channel is the pointer to the channel to work on

Returns

non zero if the channel is busy
0 is the channel is idle

References XAxiVdma_ReadReg, XAXIVDMA_SR_HALTED_MASK, XAXIVDMA_SR_IDLE_MASK, and XAXIVDMA_SR_OFFSET.

Referenced by XAxiVdma_ChannelConfig(), XAxiVdma_ChannelSetBdAddrs(), XAxiVdma_ChannelStart(), XAxiVdma_ChannelStartTransfer(), and XAxiVdma_IsBusy().

void XAxiVdma_ChannelRegisterDump ( XAxiVdma_Channel * Channel )

Dump registers from one DMA channel.

Parameters

Channel is the pointer to the channel to work on

Returns: None

References XAXIVDMA_CDESC_OFFSET, XAXIVDMA_CR_OFFSET, XAxiVdma_ReadReg, XAXIVDMA_SR_OFFSET, and XAXIVDMA_TDESC_OFFSET.

Referenced by XAxiVdma_DmaRegisterDump().

void XAxiVdma_ChannelReset ( XAxiVdma_Channel * Channel )

This function resets one DMA channel.

The registers will be default values after the reset

Parameters

Channel is the pointer to the DMA channel to work on

Returns: None

References XAXIVDMA_CR_OFFSET, XAXIVDMA_CR_RESET_MASK, and XAxiVdma_WriteReg.

Referenced by XAxiVdma_CfgInitialize(), XAxiVdma_Reset(), and XAxiVdma_Selftest().

int XAxiVdma_ChannelResetNotDone ( XAxiVdma_Channel * Channel )

This function checks whether reset operation is done.

Parameters

Channel is the pointer to the DMA channel to work on

Returns

0 if reset is done
1 if reset is still going

References XAXIVDMA_CR_OFFSET, XAXIVDMA_CR_RESET_MASK, and XAxiVdma_ReadReg.

Referenced by XAxiVdma_CfgInitialize(), XAxiVdma_ResetNotDone(), and XAxiVdma_Selftest().

int XAxiVdma_ChannelSetBdAddrs	(	XAxiVdma_Channel *	Channel,
		UINTPTR	BdAddrPhys,
		UINTPTR	BdAddrVirt
	)

Setup BD addresses to a different memory region.

In some systems, it is convenient to put BDs into a certain region of the memory. This function enables that.

Parameters

Channel	is the pointer to the channel to work on
BdAddrPhys	is the physical starting address for BDs
BdAddrVirt	is the Virtual starting address for BDs. For systems that do not use MMU, then virtual address is the same as physical address

Returns

XST_SUCCESS for a successful setup
XST_DEVICE_BUSY if the DMA channel is not idle, BDs are still being used

We assume that the memory region starting from BdAddrPhys is large enough to hold all the BDs.

References XAxiVdma_ChannelIsBusy().

Referenced by XAxiVdma_SetBdAddrs().

int XAxiVdma_ChannelSetBufferAddr	(	XAxiVdma_Channel *	Channel,
		UINTPTR *	BufferAddrSet,
		int	NumFrames
	)

Configure buffer addresses for one DMA channel.

The buffer addresses are physical addresses. Access to 32 Frame Buffer Addresses in direct mode is done through XAxiVdma_ChannelHiFrmAddrEnable/Disable Functions. 0 - Access Bank0 Registers (0x5C - 0x98) 1 - Access Bank1 Registers (0x5C - 0x98)

Parameters

Channel	is the pointer to the channel to work on
BufferAddrSet	is the set of addresses for the transfers
NumFrames	is the number of frames to set the address

Returns

XST_SUCCESS if successful
XST_FAILURE if channel has not being initialized
XST_DEVICE_BUSY if the DMA channel is not idle, BDs are still being used
XST_INVAID_PARAM if buffer address not valid, for example, unaligned address with no DRE built in the hardware

References XAxiVdma_ChannelHiFrmAddrDisable, XAxiVdma_ChannelHiFrmAddrEnable, XAXIVDMA_MAX_FRAMESTORE, XAXIVDMA_MAX_FRAMESTORE_64, XAXIVDMA_START_ADDR_LEN, XAXIVDMA_START_ADDR_MSB_OFFSET, XAXIVDMA_START_ADDR_OFFSET, and XAxiVdma_WriteReg.

Referenced by XAxiVdma_ChannelStartTransfer(), and XAxiVdma_DmaSetBufferAddr().

int XAxiVdma_ChannelSetFrmCnt	(	XAxiVdma_Channel *	Channel,
		u8	FrmCnt,
		u8	DlyCnt
	)

Set the frame counter and delay counter for one channel.

Parameters

Channel	is the pointer to the channel to work on
FrmCnt	is the frame counter value to be set
DlyCnt	is the delay counter value to be set

Returns

XST_SUCCESS if setup finishes successfully
XST_FAILURE if channel is not initialized
XST_INVALID_PARAM if the configuration structure has invalid values
XST_NO_FEATURE if Frame Counter or Delay Counter is disabled

References XAXIVDMA_CR_OFFSET, XAXIVDMA_DELAY_MASK, XAXIVDMA_FRMCNT_MASK, XAxiVdma_ReadReg, and XAxiVdma_WriteReg.

Referenced by XAxiVdma_SetFrameCounter().

int XAxiVdma_ChannelStart ( XAxiVdma_Channel * Channel )

Start one DMA channel.

Parameters

Channel is the pointer to the channel to work on

Returns

XST_SUCCESS if successful
XST_FAILURE if channel is not initialized
XST_DMA_ERROR if: . The DMA channel fails to stop . The DMA channel fails to start
XST_DEVICE_BUSY is the channel is doing transfers

References XAXIVDMA_CDESC_OFFSET, XAxiVdma_ChannelIsBusy(), XAXIVDMA_CR_OFFSET, XAXIVDMA_CR_RUNSTOP_MASK, XAxiVdma_ReadReg, XAXIVDMA_TDESC_OFFSET, XAXIVDMA_VSIZE_OFFSET, and XAxiVdma_WriteReg.

Referenced by XAxiVdma_ChannelStartTransfer(), and XAxiVdma_DmaStart().

void XAxiVdma_ChannelStartFrmCntEnable ( XAxiVdma_Channel * Channel )

Set the channel to run in frame count enable mode.

Parameters

Channel is the pointer to the channel to work on

Returns: None

References XAXIVDMA_CR_FRMCNT_EN_MASK, XAXIVDMA_CR_OFFSET, XAxiVdma_ReadReg, and XAxiVdma_WriteReg.

Referenced by XAxiVdma_StartFrmCntEnable().

int XAxiVdma_ChannelStartParking ( XAxiVdma_Channel * Channel )

Set the channel to run in parking mode.

Parameters

Channel is the pointer to the channel to work on

Returns

XST_SUCCESS if everything is fine
XST_FAILURE if hardware is not running

References XAXIVDMA_CR_OFFSET, XAXIVDMA_CR_TAIL_EN_MASK, XAxiVdma_ReadReg, and XAxiVdma_WriteReg.

Referenced by XAxiVdma_StartParking().

int XAxiVdma_ChannelStartTransfer	(	XAxiVdma_Channel *	Channel,
		XAxiVdma_ChannelSetup *	ChannelCfgPtr
	)

Start a transfer.

This function setup the DMA engine and start the engine to do the transfer.

Parameters

Channel	is the pointer to the channel to work on
ChannelCfgPtr	is the pointer to the setup structure

Returns

XST_SUCCESS for a successful submission
XST_FAILURE if channel has not being initialized
XST_DEVICE_BUSY if the DMA channel is not idle, BDs are still being used
XST_INVAID_PARAM if parameters in config structure not valid

References XAxiVdma_ChannelConfig(), XAxiVdma_ChannelIsBusy(), XAxiVdma_ChannelSetBufferAddr(), and XAxiVdma_ChannelStart().

Referenced by XAxiVdma_StartReadFrame(), and XAxiVdma_StartWriteFrame().

void XAxiVdma_ChannelStop ( XAxiVdma_Channel * Channel )

Stop one DMA channel.

Parameters

Channel is the pointer to the channel to work on

Returns: None

References XAXIVDMA_CR_OFFSET, XAXIVDMA_CR_RUNSTOP_MASK, XAxiVdma_ReadReg, and XAxiVdma_WriteReg.

Referenced by XAxiVdma_DmaStop().

void XAxiVdma_ChannelStopParking ( XAxiVdma_Channel * Channel )

Set the channel to run in circular mode, exiting parking mode.

Parameters

Channel is the pointer to the channel to work on

Returns: None

References XAXIVDMA_CR_OFFSET, XAXIVDMA_CR_TAIL_EN_MASK, XAxiVdma_ReadReg, and XAxiVdma_WriteReg.

Referenced by XAxiVdma_StopParking().

int XAxiVdma_ClearDmaChannelErrors	(	XAxiVdma *	InstancePtr,
		u16	Direction,
		u32	ErrorMask
	)

Clear DMA Channel Errors.

Parameters

InstancePtr	is the XAxiVdma instance to operate on
Direction	is the channel to work on, use XAXIVDMA_READ/WRITE
ErrorMask	is the mask of error bits to clear

Returns

- XST_SUCCESS, when error bits are cleared.

XST_INVALID_PARAM, when channel pointer is invalid.
XST_DEVICE_NOT_FOUND, when the channel is not valid.

Note: None

References XAxiVdma_GetChannel().

u32 XAxiVdma_CurrFrameStore	(	XAxiVdma *	InstancePtr,
		u16	Direction
	)

Get the current frame that hardware is working on.

Parameters

InstancePtr	is the pointer to the DMA engine to work on
Direction	is the channel to work on, use XAXIVDMA_READ/WRITE

Returns: The current frame that the hardware is working on

Note: If returned frame number is out of range, then the channel is invalid

References XAxiVdma::BaseAddr, XAXIVDMA_PARKPTR_OFFSET, XAXIVDMA_PARKPTR_READSTR_MASK, XAXIVDMA_PARKPTR_WRTSTR_MASK, XAXIVDMA_READ, XAxiVdma_ReadReg, and XAXIVDMA_WRITE.

int XAxiVdma_DmaConfig	(	XAxiVdma *	InstancePtr,
		u16	Direction,
		XAxiVdma_DmaSetup *	DmaConfigPtr
	)

Configure one DMA channel using the configuration structure.

Parameters

InstancePtr	is the pointer to the DMA engine to work on
Direction	is the DMA channel to work on
DmaConfigPtr	is the pointer to the setup structure

Returns

XST_SUCCESS if successful
XST_DEVICE_BUSY if the DMA channel is not idle, BDs are still being used
XST_INVAID_PARAM if buffer address not valid, for example, unaligned address with no DRE built in the hardware, or Direction invalid
XST_DEVICE_NOT_FOUND if the channel is invalid

References XAxiVdma_ChannelConfig(), and XAxiVdma_GetChannel().

void XAxiVdma_DmaRegisterDump	(	XAxiVdma *	InstancePtr,
		u16	Direction
	)

Dump registers of one DMA channel.

Parameters

InstancePtr	is the pointer to the DMA engine to work on
Direction	is the DMA channel to work on

Returns: None

Note: If channel is invalid, then do nothing on that channel

References XAxiVdma_ChannelRegisterDump(), and XAxiVdma_GetChannel().

int XAxiVdma_DmaSetBufferAddr	(	XAxiVdma *	InstancePtr,
		u16	Direction,
		UINTPTR *	BufferAddrSet
	)

Configure buffer addresses for one DMA channel.

Parameters

InstancePtr	is the pointer to the DMA engine to work on
Direction	is the DMA channel to work on
BufferAddrSet	is the set of addresses for the transfers

Returns

XST_SUCCESS if successful
XST_DEVICE_BUSY if the DMA channel is not idle, BDs are still being used
XST_INVAID_PARAM if buffer address not valid, for example, unaligned address with no DRE built in the hardware, or Direction invalid
XST_DEVICE_NOT_FOUND if the channel is invalid

References XAxiVdma_ChannelSetBufferAddr(), and XAxiVdma_GetChannel().

int XAxiVdma_DmaStart	(	XAxiVdma *	InstancePtr,
		u16	Direction
	)

Start one DMA channel.

Parameters

InstancePtr	is the pointer to the DMA engine to work on
Direction	is the DMA channel to work on

Returns

XST_SUCCESS if channel started successfully
XST_FAILURE otherwise
XST_DEVICE_NOT_FOUND if the channel is invalid
XST_INVALID_PARAM if Direction invalid

References XAxiVdma_ChannelStart(), and XAxiVdma_GetChannel().

void XAxiVdma_DmaStop	(	XAxiVdma *	InstancePtr,
		u16	Direction
	)

Stop one DMA channel.

Parameters

InstancePtr	is the pointer to the DMA engine to work on
Direction	is the DMA channel to work on

Returns: None

Note: If channel is invalid, then do nothing on that channel

References XAxiVdma_ChannelStop(), and XAxiVdma_GetChannel().

int XAxiVdma_FsyncSrcSelect	(	XAxiVdma *	InstancePtr,
		u32	Source,
		u16	Direction
	)

Configure Frame Sync Source and valid only when C_USE_FSYNC is enabled.

Parameters

InstancePtr	is the pointer to the DMA engine to work on
Source	is the value to set the source of Frame Sync
Direction	is the DMA channel to work on

Returns

XST_SUCCESS if successful
XST_FAILURE if C_USE_FSYNC is disabled.

References XAxiVdma::UseFsync, XAXIVDMA_CHAN_FSYNC, XAXIVDMA_CR_FSYNC_SRC_MASK, XAXIVDMA_CR_OFFSET, XAxiVdma_GetChannel(), XAxiVdma_ReadReg, XAXIVDMA_WRITE, and XAxiVdma_WriteReg.

int XAxiVdma_GenLockSourceSelect	(	XAxiVdma *	InstancePtr,
		u32	Source,
		u16	Direction
	)

Configure Gen Lock Source.

Parameters

InstancePtr	is the pointer to the DMA engine to work on
Source	is the value to set the source of Gen Lock
Direction	is the DMA channel to work on

Returns

XST_SUCCESS if successful
XST_FAILURE if the channel is in GenLock Master Mode. if C_INCLUDE_INTERNAL_GENLOCK is disabled.

References XAxiVdma::HasMm2S, XAxiVdma::HasS2Mm, XAxiVdma::InternalGenLock, XAXIVDMA_CR_GENLCK_SRC_MASK, XAXIVDMA_CR_OFFSET, XAXIVDMA_EXTERNAL_GENLOCK, XAXIVDMA_GENLOCK_MASTER, XAxiVdma_GetChannel(), XAXIVDMA_READ, XAxiVdma_ReadReg, XAXIVDMA_WRITE, and XAxiVdma_WriteReg.

XAxiVdma_Channel * XAxiVdma_GetChannel	(	XAxiVdma *	InstancePtr,
		u16	Direction
	)

Get a channel.

Parameters

InstancePtr	is the DMA engine to work on
Direction	is the direction for the channel to get

Returns: The pointer to the channel. Upon error, return NULL.

Note: Since this function is internally used, we assume Direction is valid

References XAxiVdma::ReadChannel, XAxiVdma::WriteChannel, XAXIVDMA_READ, and XAXIVDMA_WRITE.

Referenced by XAxiVdma_CfgInitialize(), XAxiVdma_ClearDmaChannelErrors(), XAxiVdma_DmaConfig(), XAxiVdma_DmaRegisterDump(), XAxiVdma_DmaSetBufferAddr(), XAxiVdma_DmaStart(), XAxiVdma_DmaStop(), XAxiVdma_FsyncSrcSelect(), XAxiVdma_GenLockSourceSelect(), XAxiVdma_GetDmaChannelErrors(), XAxiVdma_GetFrameCounter(), XAxiVdma_GetFrmStore(), XAxiVdma_GetStatus(), XAxiVdma_IntrClear(), XAxiVdma_IntrDisable(), XAxiVdma_IntrEnable(), XAxiVdma_IntrGetPending(), XAxiVdma_IsBusy(), XAxiVdma_MaskS2MMErrIntr(), XAxiVdma_ReadIntrHandler(), XAxiVdma_Reset(), XAxiVdma_ResetNotDone(), XAxiVdma_Selftest(), XAxiVdma_SetBdAddrs(), XAxiVdma_SetFrameCounter(), XAxiVdma_SetFrmStore(), XAxiVdma_SetLineBufThreshold(), XAxiVdma_StartFrmCntEnable(), XAxiVdma_StartParking(), XAxiVdma_StartReadFrame(), XAxiVdma_StartWriteFrame(), XAxiVdma_StopParking(), and XAxiVdma_WriteIntrHandler().

int XAxiVdma_GetDmaChannelErrors	(	XAxiVdma *	InstancePtr,
		u16	Direction
	)

Check for DMA Channel Errors.

Parameters

InstancePtr	is the XAxiVdma instance to operate on
Direction	is the channel to work on, use XAXIVDMA_READ/WRITE

Returns

- Errors seen on the channel

XST_INVALID_PARAM, when channel pointer is invalid.
XST_DEVICE_NOT_FOUND, when the channel is not valid.

Note: None

References XAxiVdma_GetChannel().

void XAxiVdma_GetFrameCounter	(	XAxiVdma *	InstancePtr,
		XAxiVdma_FrameCounter *	CfgPtr
	)

Get the frame counter and delay counter for both channels.

Parameters

InstancePtr	is the pointer to the DMA engine to work on
CfgPtr	is the configuration structure to contain return values

Returns: None

Note: If returned frame counter value is 0, then the channel is not valid

References XAxiVdma::IsReady, XAxiVdma_FrameCounter::ReadDelayTimerCount, XAxiVdma_FrameCounter::ReadFrameCount, XAxiVdma_FrameCounter::WriteDelayTimerCount, XAxiVdma_FrameCounter::WriteFrameCount, XAxiVdma_ChannelGetFrmCnt(), XAXIVDMA_DEVICE_READY, XAxiVdma_GetChannel(), XAXIVDMA_READ, and XAXIVDMA_WRITE.

void XAxiVdma_GetFrmStore	(	XAxiVdma *	InstancePtr,
		u8 *	FrmStoreNum,
		u16	Direction
	)

Get the number of frame store buffers to use.

Parameters

InstancePtr	is the XAxiVdma instance to operate on
FrmStoreNum	is the number of frame store buffers to use.
Direction	is the channel to work on, use XAXIVDMA_READ/WRITE

Returns: None

Note: None

References XAXIVDMA_FRMSTORE_OFFSET, XAxiVdma_GetChannel(), and XAxiVdma_ReadReg.

u32 XAxiVdma_GetStatus	(	XAxiVdma *	InstancePtr,
		u16	Direction
	)

Get the status of a channel.

Parameters

InstancePtr	is the pointer to the DMA engine to work on
Direction	is the channel to work on, use XAXIVDMA_READ/WRITE

Returns: The status of the channel

Note: An invalid return value indicates that channel is invalid

References XAxiVdma_ChannelGetStatus(), and XAxiVdma_GetChannel().

Referenced by main().

u32 XAxiVdma_GetVersion ( XAxiVdma * InstancePtr )

Get the version of the hardware.

Parameters

InstancePtr is the pointer to the DMA engine to work on

Returns: The version of the hardware

References XAxiVdma::BaseAddr, XAxiVdma_ReadReg, and XAXIVDMA_VERSION_OFFSET.

void XAxiVdma_IntrClear	(	XAxiVdma *	InstancePtr,
		u32	IntrType,
		u16	Direction
	)

Clear the pending interrupts specified by the bit mask.

Interrupts not specified by the mask will not be affected

Parameters

InstancePtr	is the pointer to the DMA engine to work on
Direction	is the DMA channel, use XAXIVDMA_READ or XAXIVDMA_WRITE
IntrType	is the bit mask for the interrupts to be cleared

Returns: None

Note: If channel is invalid, then nothing is done

References XAxiVdma_ChannelIntrClear(), and XAxiVdma_GetChannel().

void XAxiVdma_IntrDisable	(	XAxiVdma *	InstancePtr,
		u32	IntrType,
		u16	Direction
	)

Disable specific interrupts for a channel.

Interrupts not specified by the mask will not be affected

Parameters

InstancePtr	is the pointer to the DMA engine to work on
IntrType	is the bit mask for the interrupts to be disabled
Direction	is the DMA channel, use XAXIVDMA_READ or XAXIVDMA_WRITE

Returns: None

Note: If channel is invalid, then nothing is done

References XAxiVdma_ChannelDisableIntr(), and XAxiVdma_GetChannel().

void XAxiVdma_IntrEnable	(	XAxiVdma *	InstancePtr,
		u32	IntrType,
		u16	Direction
	)

Enable specific interrupts for a channel.

Interrupts not specified by the mask will not be affected

Parameters

InstancePtr	is the pointer to the DMA engine to work on
Direction	is the DMA channel, use XAXIVDMA_READ or XAXIVDMA_WRITE
IntrType	is the bit mask for the interrupts to be enabled

Returns: None

Note: If channel is invalid, then nothing is done

References XAxiVdma_ChannelEnableIntr(), and XAxiVdma_GetChannel().

Referenced by main(), and run_triple_frame_buffer().

u32 XAxiVdma_IntrGetPending	(	XAxiVdma *	InstancePtr,
		u16	Direction
	)

Get the pending interrupts of a channel.

Parameters

InstancePtr	is the pointer to the DMA engine to work on
Direction	is the DMA channel, use XAXIVDMA_READ or XAXIVDMA_WRITE

Returns: The bit mask for the currently pending interrupts

Note: If Direction is invalid, return 0

References XAxiVdma_ChannelGetPendingIntr(), and XAxiVdma_GetChannel().

int XAxiVdma_IsBusy	(	XAxiVdma *	InstancePtr,
		u16	Direction
	)

Check whether a DMA channel is busy.

Parameters

InstancePtr	is the pointer to the DMA engine to work on
Direction	is the channel to work on, use XAXIVDMA_READ/WRITE

Returns

Non-zero if the channel is busy
Zero if the channel is idle

References XAxiVdma_ChannelIsBusy(), and XAxiVdma_GetChannel().

XAxiVdma_Config * XAxiVdma_LookupConfig ( u16 DeviceId )

Look up the hardware configuration for a device instance.

Parameters

DeviceId is the unique device ID of the device to lookup for

Returns: The configuration structure for the device. If the device ID is not found, a NULL pointer is returned.

Referenced by AxiVDMASelfTestExample(), main(), and run_triple_frame_buffer().

int XAxiVdma_MaskS2MMErrIntr	(	XAxiVdma *	InstancePtr,
		u32	ErrorMask,
		u16	Direction
	)

Masks the S2MM error interrupt for the provided error mask value.

Parameters

InstancePtr	is the XAxiVdma instance to operate on
ErrorMask	is the mask of error bits for which S2MM error interrupt can be disabled.
Direction	is the channel to work on, use XAXIVDMA_READ/WRITE

Returns

- XST_SUCCESS, when error bits are cleared.

XST_INVALID_PARAM, when channel pointer is invalid.
XST_DEVICE_NOT_FOUND, when the channel is not valid.

Note: The register S2MM_DMA_IRQ_MASK is only applicable from IPv6.01a which is added at offset XAXIVDMA_S2MM_DMA_IRQ_MASK_OFFSET. For older versions, this offset location is reserved and so the API does not have any effect.

References XAxiVdma_GetChannel(), XAXIVDMA_S2MM_DMA_IRQ_MASK_OFFSET, XAXIVDMA_S2MM_IRQ_ERR_ALL_MASK, XAXIVDMA_WRITE, and XAxiVdma_WriteReg.

void XAxiVdma_ReadIntrHandler ( void * InstancePtr )

Interrupt handler for the read channel.

Parameters

InstancePtr is the pointer to the DMA engine to work on

Returns: None

Note: If the channel is invalid, then no interrupt handling

References XAxiVdma_ChannelCallBack::CompletionCallBack, XAxiVdma_ChannelCallBack::CompletionRef, XAxiVdma_ChannelCallBack::ErrCallBack, XAxiVdma_ChannelCallBack::ErrRef, XAxiVdma::ReadCallBack, XAxiVdma_ChannelGetEnabledIntr(), XAxiVdma_ChannelGetPendingIntr(), XAxiVdma_ChannelIntrClear(), XAxiVdma_GetChannel(), XAXIVDMA_IXR_COMPLETION_MASK, XAXIVDMA_IXR_ERROR_MASK, and XAXIVDMA_READ.

Referenced by main().

void XAxiVdma_Reset	(	XAxiVdma *	InstancePtr,
		u16	Direction
	)

This function resets one DMA channel.

The registers will be default values after the reset

Parameters

InstancePtr	is the pointer to the DMA engine to work on
Direction	is the channel to work on, use XAXIVDMA_READ/WRITE

Returns: None

Note: Due to undeterminism of system delays, check the reset status through XAxiVdma_ResetNotDone(). If direction is invalid, do nothing.

References XAxiVdma_ChannelReset(), and XAxiVdma_GetChannel().

Referenced by main().

int XAxiVdma_ResetNotDone	(	XAxiVdma *	InstancePtr,
		u16	Direction
	)

This function checks one DMA channel for reset completion.

Parameters

InstancePtr	is the pointer to the DMA engine to work on
Direction	is the channel to work on, use XAXIVDMA_READ/WRITE

Returns

0 if reset is done
1 if reset is ongoing

Note: We do not check for channel validity, because channel is marked as invalid before reset is done

References XAxiVdma_ChannelResetNotDone(), and XAxiVdma_GetChannel().

Referenced by main().

int XAxiVdma_Selftest ( XAxiVdma * InstancePtr )

Runs a self-test on the driver/device.

This test perform a reset of the VDMA device and checks the device is coming out of reset or not

Parameters

InstancePtr is a pointer to the XAxiVdma instance.

Returns

XST_SUCCESS if self-test was successful

XST_FAILURE if the device is not coming out of reset.

Note: None.

References XAxiVdma::BaseAddr, XAxiVdma::HasMm2S, XAxiVdma::HasS2Mm, XAxiVdma_ChannelReset(), XAxiVdma_ChannelResetNotDone(), XAxiVdma_GetChannel(), XAXIVDMA_READ, XAXIVDMA_RX_OFFSET, XAXIVDMA_TX_OFFSET, and XAXIVDMA_WRITE.

Referenced by AxiVDMASelfTestExample().

int XAxiVdma_SetBdAddrs	(	XAxiVdma *	InstancePtr,
		u32	BdAddrPhys,
		u32	BdAddrVirt,
		int	NumBds,
		u16	Direction
	)

Set BD addresses to be different.

In some systems, it is convenient to put BDs into a certain region of the memory. This function enables that.

Parameters

InstancePtr	is the pointer to the DMA engine to work on
BdAddrPhys	is the physical starting address for BDs
BdAddrVirt	is the Virtual starting address for BDs. For systems that do not use MMU, then virtual address is the same as physical address
NumBds	is the number of BDs to setup with. This is required to be the same as the number of frame stores for that channel
Direction	is the channel direction

Returns

XST_SUCCESS for a successful setup
XST_DEVICE_BUSY if the DMA channel is not idle, BDs are still being used
XST_INVALID_PARAM if parameters not valid
XST_DEVICE_NOT_FOUND if the channel is invalid

We assume that the memory region starting from BdAddrPhys and BdAddrVirt are large enough to hold all the BDs.

References XAXIVDMA_BD_MINIMUM_ALIGNMENT, XAxiVdma_ChannelSetBdAddrs(), and XAxiVdma_GetChannel().

int XAxiVdma_SetCallBack	(	XAxiVdma *	InstancePtr,
		u32	HandlerType,
		void *	CallBackFunc,
		void *	CallBackRef,
		u16	Direction
	)

Set call back function and call back reference pointer for one channel.

Parameters

InstancePtr	is the pointer to the DMA engine to work on
HandlerType	is the interrupt type that this callback handles
CallBackFunc	is the call back function pointer
CallBackRef	is the call back reference pointer
Direction	is the DMA channel, use XAXIVDMA_READ or XAXIVDMA_WRITE

Returns

XST_SUCCESS if everything is fine
XST_INVALID_PARAM if the handler type or direction invalid

Note: This function overwrites the existing interrupt handler and its reference pointer. The function sets the handlers even if the channels are invalid.

References XAxiVdma_ChannelCallBack::CompletionCallBack, XAxiVdma_ChannelCallBack::CompletionRef, XAxiVdma_ChannelCallBack::ErrCallBack, XAxiVdma_ChannelCallBack::ErrRef, XAxiVdma::IsReady, XAxiVdma::ReadCallBack, XAxiVdma::WriteCallBack, XAXIVDMA_DEVICE_READY, XAXIVDMA_HANDLER_ERROR, XAXIVDMA_HANDLER_GENERAL, and XAXIVDMA_READ.

Referenced by main().

int XAxiVdma_SetFrameCounter	(	XAxiVdma *	InstancePtr,
		XAxiVdma_FrameCounter *	CfgPtr
	)

Set the frame counter and delay counter for both channels.

Parameters

InstancePtr	is the pointer to the DMA engine to work on
CfgPtr	is the pointer to the configuration structure

Returns

XST_SUCCESS if setup finishes successfully
XST_INVALID_PARAM if the configuration structure has invalid values
Others if setting channel frame counter fails

Note: If channel is invalid, then do nothing on that channel

References XAxiVdma::IsReady, XAxiVdma_FrameCounter::ReadDelayTimerCount, XAxiVdma_FrameCounter::ReadFrameCount, XAxiVdma_FrameCounter::WriteDelayTimerCount, XAxiVdma_FrameCounter::WriteFrameCount, XAxiVdma_ChannelSetFrmCnt(), XAXIVDMA_DEVICE_READY, XAxiVdma_GetChannel(), XAXIVDMA_READ, and XAXIVDMA_WRITE.

Referenced by main(), and run_triple_frame_buffer().

int XAxiVdma_SetFrmStore	(	XAxiVdma *	InstancePtr,
		u8	FrmStoreNum,
		u16	Direction
	)

Set the number of frame store buffers to use.

Parameters

InstancePtr	is the XAxiVdma instance to operate on
FrmStoreNum	is the number of frame store buffers to use.
Direction	is the channel to work on, use XAXIVDMA_READ/WRITE

Returns

- XST_SUCCESS if operation is successful

XST_FAILURE if operation fails.
XST_NO_FEATURE if access to FrameStore register is disabled

Note: None

References XAxiVdma::MaxNumFrames, XAxiVdma_ChannelInit(), XAXIVDMA_FRMSTORE_OFFSET, XAxiVdma_GetChannel(), and XAxiVdma_WriteReg.

Referenced by main().

int XAxiVdma_SetLineBufThreshold	(	XAxiVdma *	InstancePtr,
		int	LineBufThreshold,
		u16	Direction
	)

Configure Line Buffer Threshold.

Parameters

InstancePtr	is the pointer to the DMA engine to work on
LineBufThreshold	is the value to set threshold
Direction	is the DMA channel to work on

Returns

XST_SUCCESS if successful
XST_FAILURE otherwise
XST_NO_FEATURE if access to Threshold register is disabled

References XAXIVDMA_BUFTHRES_OFFSET, XAXIVDMA_ENABLE_DBG_THRESHOLD_REG, XAxiVdma_GetChannel(), XAxiVdma_ReadReg, and XAxiVdma_WriteReg.

void XAxiVdma_StartFrmCntEnable	(	XAxiVdma *	InstancePtr,
		u16	Direction
	)

Start frame count enable on one channel.

This is needed to start limiting the number of frames to transfer so that software can check the data etc after hardware stops transfer.

Parameters

InstancePtr	is the pointer to the DMA engine to work on
Direction	is the channel to work on, use XAXIVDMA_READ/WRITE

Returns: None

References XAxiVdma_ChannelStartFrmCntEnable(), and XAxiVdma_GetChannel().

int XAxiVdma_StartParking	(	XAxiVdma *	InstancePtr,
		int	FrameIndex,
		u16	Direction
	)

Start parking mode on a certain frame.

Parameters

InstancePtr	is the pointer to the DMA engine to work on
FrameIndex	is the frame to park on
Direction	is the channel to work on, use XAXIVDMA_READ/WRITE

Returns

XST_SUCCESS if everything is fine
XST_INVALID_PARAM if . channel is invalid . FrameIndex is invalid . Direction is invalid

References XAxiVdma::BaseAddr, XAxiVdma_ChannelStartParking(), XAXIVDMA_FRM_MAX, XAxiVdma_GetChannel(), XAXIVDMA_PARKPTR_OFFSET, XAXIVDMA_PARKPTR_READREF_MASK, XAXIVDMA_PARKPTR_WRTREF_MASK, XAXIVDMA_READ, XAxiVdma_ReadReg, XAXIVDMA_WRITE, and XAxiVdma_WriteReg.

int XAxiVdma_StartReadFrame	(	XAxiVdma *	InstancePtr,
		XAxiVdma_DmaSetup *	DmaConfigPtr
	)

Start a read operation.

Read corresponds to send data from memory to device

Parameters

InstancePtr	is the pointer to the DMA engine to work on
DmaConfigPtr	is the pointer to the setup structure

Returns

XST_SUCCESS for a successful submission
XST_DEVICE_BUSY if the DMA channel is not idle, BDs are still being used
XST_INVAID_PARAM if parameters in config structure not valid
XST_DEVICE_NOT_FOUND if the channel is invalid

References XAxiVdma_ChannelStartTransfer(), XAxiVdma_GetChannel(), and XAXIVDMA_READ.

int XAxiVdma_StartWriteFrame	(	XAxiVdma *	InstancePtr,
		XAxiVdma_DmaSetup *	DmaConfigPtr
	)

Start a write operation.

Write corresponds to send data from device to memory

Parameters

InstancePtr	is the pointer to the DMA engine to work on
DmaConfigPtr	is the pointer to the setup structure

Returns

XST_SUCCESS for a successful submission
XST_DEVICE_BUSY if the DMA channel is not idle, BDs are still being used
XST_INVAID_PARAM if parameters in config structure not valid
XST_DEVICE_NOT_FOUND if the channel is invalid

References XAxiVdma_ChannelStartTransfer(), XAxiVdma_GetChannel(), and XAXIVDMA_WRITE.

void XAxiVdma_StopParking	(	XAxiVdma *	InstancePtr,
		u16	Direction
	)

Exit parking mode, the channel will return to circular buffer mode.

Parameters

InstancePtr	is the pointer to the DMA engine to work on
Direction	is the channel to work on, use XAXIVDMA_READ/WRITE

Returns: None

Note: If channel is invalid, then do nothing

References XAxiVdma_ChannelStopParking(), and XAxiVdma_GetChannel().

void XAxiVdma_WriteIntrHandler ( void * InstancePtr )

Interrupt handler for the write channel.

Parameters

InstancePtr is the pointer to the DMA engine to work on

Returns: None

Note: If the channel is invalid, then no interrupt handling

References XAxiVdma_ChannelCallBack::CompletionCallBack, XAxiVdma_ChannelCallBack::CompletionRef, XAxiVdma_ChannelCallBack::ErrCallBack, XAxiVdma_ChannelCallBack::ErrRef, XAxiVdma::WriteCallBack, XAxiVdma_ChannelGetEnabledIntr(), XAxiVdma_ChannelGetPendingIntr(), XAxiVdma_ChannelIntrClear(), XAxiVdma_GetChannel(), XAXIVDMA_IXR_COMPLETION_MASK, XAXIVDMA_IXR_ERROR_MASK, and XAXIVDMA_WRITE.

Referenced by main().

Variable Documentation

int XAxiVdma_Config::AddrWidth

Address Width.

Referenced by XAxiVdma_CfgInitialize().

int XAxiVdma::AddrWidth

Address Width.

Referenced by XAxiVdma_CfgInitialize().

UINTPTR XAxiVdma::BaseAddr

Memory address for this device.

Referenced by XAxiVdma_CfgInitialize(), XAxiVdma_CurrFrameStore(), XAxiVdma_GetVersion(), XAxiVdma_Selftest(), and XAxiVdma_StartParking().

UINTPTR XAxiVdma_Config::BaseAddress

    BaseAddress is the physical base address of the

device's registers

Referenced by AxiVDMASelfTestExample(), main(), and run_triple_frame_buffer().

XAxiVdma_CallBack XAxiVdma_ChannelCallBack::CompletionCallBack

Call back for completion intr.

Referenced by XAxiVdma_CfgInitialize(), XAxiVdma_ReadIntrHandler(), XAxiVdma_SetCallBack(), and XAxiVdma_WriteIntrHandler().

void* XAxiVdma_ChannelCallBack::CompletionRef

Call back ref.

Referenced by XAxiVdma_ReadIntrHandler(), XAxiVdma_SetCallBack(), and XAxiVdma_WriteIntrHandler().

u16 XAxiVdma_Config::DeviceId

DeviceId is the unique ID of the device.

int XAxiVdma_Config::EnableAllDbgFeatures

Enable all Debug features This corresponds to C_ENABLE_DEBUG_ALL configuration parameter.

Referenced by XAxiVdma_CfgInitialize().

int XAxiVdma_DmaSetup::EnableCircularBuf

Circular Buffer Mode?

int XAxiVdma_DmaSetup::EnableFrameCounter

Frame Counter Enable.

int XAxiVdma_DmaSetup::EnableSync

Gen-Lock Mode?

u8 XAxiVdma_DmaSetup::EnableVFlip

Vertical Flip state.

int XAxiVdma_Config::EnableVIDParamRead

Read Enable for video parameters in direct register mode.

int XAxiVdma::EnableVIDParamRead

Read Enable for video parameters in direct register mode.

XAxiVdma_ErrorCallBack XAxiVdma_ChannelCallBack::ErrCallBack

Call back for error intr.

Referenced by XAxiVdma_CfgInitialize(), XAxiVdma_ReadIntrHandler(), XAxiVdma_SetCallBack(), and XAxiVdma_WriteIntrHandler().

void* XAxiVdma_ChannelCallBack::ErrRef

Call back ref.

Referenced by XAxiVdma_ReadIntrHandler(), XAxiVdma_SetCallBack(), and XAxiVdma_WriteIntrHandler().

int XAxiVdma_DmaSetup::FixedFrameStoreAddr

Fixed Frame Store Address index.

int XAxiVdma_Config::FlushonFsync

   VDMA Transactions are flushed & channel states

reset on Frame Sync

Referenced by XAxiVdma_CfgInitialize().

int XAxiVdma_DmaSetup::FrameDelay

Frame Delay.

UINTPTR XAxiVdma_DmaSetup::FrameStoreStartAddr[XAXIVDMA_MAX_FRAMESTORE]

Start Addresses of Frame Store Buffers.

int XAxiVdma_DmaSetup::GenLockRepeat

Gen-Lock Repeat?

int XAxiVdma_Config::HasMm2S

Whether hw build has read channel.

Referenced by XAxiVdma_CfgInitialize().

int XAxiVdma::HasMm2S

Whether hw build has read channel.

Referenced by XAxiVdma_CfgInitialize(), XAxiVdma_GenLockSourceSelect(), and XAxiVdma_Selftest().

int XAxiVdma_Config::HasMm2SDRE

Read channel supports unaligned transfer.

Referenced by XAxiVdma_CfgInitialize().

int XAxiVdma::HasMm2SDRE

Whether read channel has DRE.

int XAxiVdma_Config::HasS2Mm

Whether hw build has write channel.

Referenced by XAxiVdma_CfgInitialize().

int XAxiVdma::HasS2Mm

Whether hw build has write channel.

Referenced by XAxiVdma_CfgInitialize(), XAxiVdma_GenLockSourceSelect(), and XAxiVdma_Selftest().

int XAxiVdma_Config::HasS2MmDRE

Write channel supports unaligned transfer.

Referenced by XAxiVdma_CfgInitialize().

int XAxiVdma::HasS2MmDRE

Whether write channel has DRE.

int XAxiVdma_Config::HasSG

Whether hardware has SG engine.

Referenced by XAxiVdma_CfgInitialize().

int XAxiVdma::HasSG

Whether hardware has SG engine.

Referenced by XAxiVdma_CfgInitialize().

u8 XAxiVdma_Config::HasVFlip

Whether hardware has Vertical Flip enabled(c_enable_vert_flip)

Referenced by XAxiVdma_CfgInitialize().

int XAxiVdma_DmaSetup::HoriSizeInput

Horizontal size input.

int XAxiVdma_Config::InternalGenLock

Internal Gen Lock.

Referenced by XAxiVdma_CfgInitialize().

int XAxiVdma::InternalGenLock

Internal Gen Lock.

Referenced by XAxiVdma_CfgInitialize(), and XAxiVdma_GenLockSourceSelect().

UINTPTR XAxiVdma_Config::IntrParent

Bits[11:0] Interrupt-id Bits[15:12] trigger type and level flags.

Referenced by main().

int XAxiVdma::IsReady

Whether driver is initialized.

Referenced by XAxiVdma_CfgInitialize(), XAxiVdma_GetFrameCounter(), XAxiVdma_SetCallBack(), and XAxiVdma_SetFrameCounter().

u16 XAxiVdma_Config::MaxFrameStoreNum

The maximum number of Frame Stores.

Referenced by main(), and XAxiVdma_CfgInitialize().

int XAxiVdma::MaxNumFrames

Number of frames to work on.

Referenced by XAxiVdma_CfgInitialize(), and XAxiVdma_SetFrmStore().

int XAxiVdma_Config::Mm2SBufDepth

Depth of Read Channel Line Buffer FIFO.

Referenced by XAxiVdma_CfgInitialize().

int XAxiVdma_Config::Mm2SDlyCntrEn

MM2S Delay Counter (Control Reg) Enable Flag This corresponds to C_ENABLE_DEBUG_INFO_6 configuration parameter.

Referenced by XAxiVdma_CfgInitialize().

int XAxiVdma_Config::Mm2SFrmCntrEn

MM2S Frame Counter (Control Reg) Enable Flag This corresponds to C_ENABLE_DEBUG_INFO_7 configuration parameter.

Referenced by XAxiVdma_CfgInitialize().

int XAxiVdma_Config::Mm2SFrmStoreRegEn

MM2S Frame Store Register Enable Flag This corresponds to C_ENABLE_DEBUG_INFO_5 configuration parameter.

Referenced by XAxiVdma_CfgInitialize().

int XAxiVdma_Config::Mm2SGenLock

Mm2s Gen Lock Mode.

Referenced by XAxiVdma_CfgInitialize().

int XAxiVdma_Config::Mm2SStreamWidth

MM2S TData Width.

Referenced by run_triple_frame_buffer(), and XAxiVdma_CfgInitialize().

int XAxiVdma_Config::Mm2SThresRegEn

MM2S Threshold Register Enable Flag This corresponds to C_ENABLE_DEBUG_INFO_1 configuration parameter.

Referenced by XAxiVdma_CfgInitialize().

int XAxiVdma_Config::Mm2SWordLen

Read channel word length.

Referenced by XAxiVdma_CfgInitialize().

int XAxiVdma_DmaSetup::PointNum

Master we synchronize with.

XAxiVdma_ChannelCallBack XAxiVdma::ReadCallBack

Call back for read channel.

Referenced by XAxiVdma_CfgInitialize(), XAxiVdma_ReadIntrHandler(), and XAxiVdma_SetCallBack().

XAxiVdma_Channel XAxiVdma::ReadChannel

Channel to read from memory.

Referenced by XAxiVdma_GetChannel().

u8 XAxiVdma_FrameCounter::ReadDelayTimerCount

Delay timer threshold for receive.

Referenced by main(), run_triple_frame_buffer(), XAxiVdma_GetFrameCounter(), and XAxiVdma_SetFrameCounter().

u8 XAxiVdma_FrameCounter::ReadFrameCount

Interrupt threshold for Receive.

Referenced by main(), run_triple_frame_buffer(), XAxiVdma_GetFrameCounter(), and XAxiVdma_SetFrameCounter().

int XAxiVdma_Config::S2MmBufDepth

Depth of Write Channel Line Buffer FIFO.

Referenced by XAxiVdma_CfgInitialize().

int XAxiVdma_Config::S2MmDlyCntrEn

S2MM Delay Counter (Control Reg) Enable Flag This corresponds to C_ENABLE_DEBUG_INFO_14 configuration parameter.

Referenced by XAxiVdma_CfgInitialize().

int XAxiVdma_Config::S2MmFrmCntrEn

S2MM Frame Counter (Control Reg) Enable Flag This corresponds to C_ENABLE_DEBUG_INFO_15 configuration parameter.

Referenced by XAxiVdma_CfgInitialize().

int XAxiVdma_Config::S2MmFrmStoreRegEn

S2MM Frame Store Register Enable Flag This corresponds to C_ENABLE_DEBUG_INFO_13 configuration parameter.

Referenced by XAxiVdma_CfgInitialize().

int XAxiVdma_Config::S2MmGenLock

S2Mm Gen Lock Mode.

Referenced by XAxiVdma_CfgInitialize().

int XAxiVdma_Config::S2MmSOF

S2MM Start of Flag Enable.

Referenced by XAxiVdma_CfgInitialize().

int XAxiVdma_Config::S2MmStreamWidth

S2MM TData Width.

Referenced by XAxiVdma_CfgInitialize().

int XAxiVdma_Config::S2MmThresRegEn

S2MM Threshold Register Enable Flag This corresponds to C_ENABLE_DEBUG_INFO_9 configuration parameter.

Referenced by XAxiVdma_CfgInitialize().

int XAxiVdma_Config::S2MmWordLen

Write channel word length.

Referenced by XAxiVdma_CfgInitialize().

int XAxiVdma_DmaSetup::Stride

Stride.

int XAxiVdma_Config::UseFsync

DMA operations synchronized to Frame Sync.

Referenced by XAxiVdma_CfgInitialize().

int XAxiVdma::UseFsync

DMA operations synchronized to Frame Sync.

Referenced by XAxiVdma_CfgInitialize(), and XAxiVdma_FsyncSrcSelect().

int XAxiVdma_DmaSetup::VertSizeInput

Vertical size input.

XAxiVdma_ChannelCallBack XAxiVdma::WriteCallBack

Call back for write channel.

Referenced by XAxiVdma_CfgInitialize(), XAxiVdma_SetCallBack(), and XAxiVdma_WriteIntrHandler().

XAxiVdma_Channel XAxiVdma::WriteChannel

Channel to write to memory.

Referenced by XAxiVdma_GetChannel().

u8 XAxiVdma_FrameCounter::WriteDelayTimerCount

Delay timer threshold for transmit.

Referenced by main(), run_triple_frame_buffer(), XAxiVdma_GetFrameCounter(), and XAxiVdma_SetFrameCounter().

u8 XAxiVdma_FrameCounter::WriteFrameCount

Interrupt threshold for transmit.

Referenced by main(), run_triple_frame_buffer(), XAxiVdma_GetFrameCounter(), and XAxiVdma_SetFrameCounter().

Data Structures

Macros

Typedefs

Functions

Variables

Buffer Descriptor Alignment

Maximum transfer length

Device registers

Start Addresses Register Array for a Channel

Bitmasks of the XAXIVDMA_CR_OFFSET register

Bitmasks of the XAXIVDMA_SR_OFFSET register

Bitmask for interrupts

Bitmask and shift for delay and coalesce

Bitmask for the XAXIVDMA_CDESC_OFFSET register

Bitmask for XAXIVDMA_TDESC_OFFSET register

Bitmask for XAXIVDMA_FRMSTORE_OFFSET register

Bitmask for XAXIVDMA_PARKPTR_OFFSET register

Bitmask for XAXIVDMA_VERSION_OFFSET register

Bitmask for XAXIVDMA_S2MM_IRQ_MASK_OFFSET register

Frame Delay shared by start address registers and BDs

Buffer Descriptor offsets

Macro Definition Documentation

Typedef Documentation

Function Documentation

Variable Documentation