import { toByteArray } from "./util";

export interface Logger {
  log(msg: string, ...args: unknown[]): void;
  error(msg: string, ...args: unknown[]): void;
  debug(msg: string, ...args: unknown[]): void;
}

export const baudRates = [
  115200, 128000, 153600, 230400, 460800, 500000, 921600, 1500000, 2000000,
];
export const FLASH_SIZES = {
  "512KB": 0x00,
  "256KB": 0x10,
  "1MB": 0x20,
  "2MB": 0x30,
  "4MB": 0x40,
  "2MB-c1": 0x50,
  "4MB-c1": 0x60,
  "8MB": 0x80,
  "16MB": 0x90,
};

export const ESP32_FLASH_SIZES = {
  "1MB": 0x00,
  "2MB": 0x10,
  "4MB": 0x20,
  "8MB": 0x30,
  "16MB": 0x40,
  "32MB": 0x50,
  "64MB": 0x60,
  "128MB": 0x70,
};

interface FlashSize {
  [key: number]: string;
}

export const DETECTED_FLASH_SIZES: FlashSize = {
  0x12: "256KB",
  0x13: "512KB",
  0x14: "1MB",
  0x15: "2MB",
  0x16: "4MB",
  0x17: "8MB",
  0x18: "16MB",
  0x19: "32MB",
  0x1a: "64MB",
  0x1b: "128MB",
  0x1c: "256MB",
  0x20: "64MB",
  0x21: "128MB",
  0x22: "256MB",
  0x32: "256KB",
  0x33: "512KB",
  0x34: "1MB",
  0x35: "2MB",
  0x36: "4MB",
  0x37: "8MB",
  0x38: "16MB",
  0x39: "32MB",
  0x3a: "64MB",
};

export const FLASH_WRITE_SIZE = 0x400;
export const STUB_FLASH_WRITE_SIZE = 0x4000;
export const FLASH_SECTOR_SIZE = 0x1000; // Flash sector size, minimum unit of erase.
export const ESP_ROM_BAUD = 115200;
export const USB_JTAG_SERIAL_PID = 0x1001;

export const ESP8266_SPI_REG_BASE = 0x60000200;
export const ESP8266_BASEFUSEADDR = 0x3ff00050;
export const ESP8266_MACFUSEADDR = 0x3ff00050;
export const ESP8266_SPI_USR_OFFS = 0x1c;
export const ESP8266_SPI_USR1_OFFS = 0x20;
export const ESP8266_SPI_USR2_OFFS = 0x24;
export const ESP8266_SPI_MOSI_DLEN_OFFS = -1;
export const ESP8266_SPI_MISO_DLEN_OFFS = -1;
export const ESP8266_SPI_W0_OFFS = 0x40;
export const ESP8266_UART_DATE_REG_ADDR = 0x60000078;
export const ESP8266_BOOTLOADER_FLASH_OFFSET = 0x0000;

export const ESP32_SPI_REG_BASE = 0x3ff42000;
export const ESP32_BASEFUSEADDR = 0x3ff5a000;
export const ESP32_MACFUSEADDR = 0x3ff5a000;
export const ESP32_SPI_USR_OFFS = 0x1c;
export const ESP32_SPI_USR1_OFFS = 0x20;
export const ESP32_SPI_USR2_OFFS = 0x24;
export const ESP32_SPI_MOSI_DLEN_OFFS = 0x28;
export const ESP32_SPI_MISO_DLEN_OFFS = 0x2c;
export const ESP32_SPI_W0_OFFS = 0x80;
export const ESP32_UART_DATE_REG_ADDR = 0x60000078;
export const ESP32_BOOTLOADER_FLASH_OFFSET = 0x1000;
export const ESP32_APB_CTL_DATE_ADDR = 0x3ff66000 + 0x7c;

export const ESP32S2_SPI_REG_BASE = 0x3f402000;
export const ESP32S2_BASEFUSEADDR = 0x3f41a000;
export const ESP32S2_EFUSE_BLOCK1_ADDR = ESP32S2_BASEFUSEADDR + 0x044;
export const ESP32S2_MACFUSEADDR = 0x3f41a044;
export const ESP32S2_SPI_USR_OFFS = 0x18;
export const ESP32S2_SPI_USR1_OFFS = 0x1c;
export const ESP32S2_SPI_USR2_OFFS = 0x20;
export const ESP32S2_SPI_MOSI_DLEN_OFFS = 0x24;
export const ESP32S2_SPI_MISO_DLEN_OFFS = 0x28;
export const ESP32S2_SPI_W0_OFFS = 0x58;
export const ESP32S2_UART_DATE_REG_ADDR = 0x60000078;
export const ESP32S2_BOOTLOADER_FLASH_OFFSET = 0x1000;
// ESP32-S2 RTC Watchdog Timer registers for USB-OTG reset
export const ESP32S2_RTCCNTL_BASE_REG = 0x3f408000;
export const ESP32S2_RTC_CNTL_WDTWPROTECT_REG =
  ESP32S2_RTCCNTL_BASE_REG + 0x00ac;
export const ESP32S2_RTC_CNTL_WDTCONFIG0_REG =
  ESP32S2_RTCCNTL_BASE_REG + 0x0094;
export const ESP32S2_RTC_CNTL_WDTCONFIG1_REG =
  ESP32S2_RTCCNTL_BASE_REG + 0x0098;
export const ESP32S2_RTC_CNTL_WDT_WKEY = 0x50d83aa1;
// ESP32-S2 GPIO strap register and boot mode control
export const ESP32S2_GPIO_STRAP_REG = 0x3f404038;
export const ESP32S2_GPIO_STRAP_SPI_BOOT_MASK = 1 << 3; // Not download mode
export const ESP32S2_GPIO_STRAP_VDDSPI_MASK = 1 << 4; // SPI voltage (1.8V vs 3.3V)
export const ESP32S2_RTC_CNTL_OPTION1_REG = 0x3f408128;
export const ESP32S2_RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK = 0x1; // Is download mode forced over USB?
export const ESP32S2_UARTDEV_BUF_NO = 0x3ffffd14; // Variable in ROM .bss which indicates the port in use
export const ESP32S2_UARTDEV_BUF_NO_USB_OTG = 2; // Value of the above indicating that USB-OTG is in use

export const ESP32S3_SPI_REG_BASE = 0x60002000;
export const ESP32S3_BASEFUSEADDR = 0x60007000;
export const ESP32S3_EFUSE_BLOCK1_ADDR = ESP32S3_BASEFUSEADDR + 0x044;
export const ESP32S3_MACFUSEADDR = 0x60007000 + 0x044;
export const ESP32S3_SPI_USR_OFFS = 0x18;
export const ESP32S3_SPI_USR1_OFFS = 0x1c;
export const ESP32S3_SPI_USR2_OFFS = 0x20;
export const ESP32S3_SPI_MOSI_DLEN_OFFS = 0x24;
export const ESP32S3_SPI_MISO_DLEN_OFFS = 0x28;
export const ESP32S3_SPI_W0_OFFS = 0x58;
export const ESP32S3_UART_DATE_REG_ADDR = 0x60000080;
export const ESP32S3_BOOTLOADER_FLASH_OFFSET = 0x0000;
// ESP32-S3 RTC Watchdog Timer registers for USB-OTG reset
export const ESP32S3_RTCCNTL_BASE_REG = 0x60008000;
export const ESP32S3_RTC_CNTL_WDTWPROTECT_REG =
  ESP32S3_RTCCNTL_BASE_REG + 0x00b0;
export const ESP32S3_RTC_CNTL_WDTCONFIG0_REG =
  ESP32S3_RTCCNTL_BASE_REG + 0x0098;
export const ESP32S3_RTC_CNTL_WDTCONFIG1_REG =
  ESP32S3_RTCCNTL_BASE_REG + 0x009c;
export const ESP32S3_RTC_CNTL_WDT_WKEY = 0x50d83aa1;
// ESP32-S3 GPIO strap register and boot mode control
export const ESP32S3_GPIO_STRAP_REG = 0x60004038;
export const ESP32S3_GPIO_STRAP_SPI_BOOT_MASK = 1 << 3; // Not download mode
export const ESP32S3_GPIO_STRAP_VDDSPI_MASK = 1 << 4;
export const ESP32S3_RTC_CNTL_OPTION1_REG = 0x6000812c;
export const ESP32S3_RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK = 0x1; // Is download mode forced over USB?
export const ESP32S3_UARTDEV_BUF_NO = 0x3fcef14c; // Variable in ROM .bss which indicates the port in use
export const ESP32S3_UARTDEV_BUF_NO_USB_OTG = 3; // The above var when USB-OTG is used
export const ESP32S3_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 4; // The above var when USB-JTAG/Serial is used

export const ESP32C2_SPI_REG_BASE = 0x60002000;
export const ESP32C2_BASEFUSEADDR = 0x60008800;
export const ESP32C2_EFUSE_BLOCK2_ADDR = ESP32C2_BASEFUSEADDR + 0x040;
export const ESP32C2_MACFUSEADDR = ESP32C2_BASEFUSEADDR + 0x040;
export const ESP32C2_SPI_USR_OFFS = 0x18;
export const ESP32C2_SPI_USR1_OFFS = 0x1c;
export const ESP32C2_SPI_USR2_OFFS = 0x20;
export const ESP32C2_SPI_MOSI_DLEN_OFFS = 0x24;
export const ESP32C2_SPI_MISO_DLEN_OFFS = 0x28;
export const ESP32C2_SPI_W0_OFFS = 0x58;
export const ESP32C2_UART_DATE_REG_ADDR = 0x6000007c;
export const ESP32C2_BOOTLOADER_FLASH_OFFSET = 0x0000;
// ESP32-C2 RTC Watchdog Timer registers
export const ESP32C2_RTCCNTL_BASE_REG = 0x60008000;
export const ESP32C2_RTC_CNTL_WDTWPROTECT_REG =
  ESP32C2_RTCCNTL_BASE_REG + 0x009c;
export const ESP32C2_RTC_CNTL_WDTCONFIG0_REG =
  ESP32C2_RTCCNTL_BASE_REG + 0x0084;
export const ESP32C2_RTC_CNTL_WDTCONFIG1_REG =
  ESP32C2_RTCCNTL_BASE_REG + 0x0088;
export const ESP32C2_RTC_CNTL_WDT_WKEY = 0x50d83aa1;

export const ESP32C3_SPI_REG_BASE = 0x60002000;
export const ESP32C3_BASEFUSEADDR = 0x60008800;
export const ESP32C3_EFUSE_BLOCK1_ADDR = ESP32C3_BASEFUSEADDR + 0x044;
export const ESP32C3_MACFUSEADDR = 0x60008800 + 0x044;
export const ESP32C3_SPI_USR_OFFS = 0x18;
export const ESP32C3_SPI_USR1_OFFS = 0x1c;
export const ESP32C3_SPI_USR2_OFFS = 0x20;
export const ESP32C3_SPI_MOSI_DLEN_OFFS = 0x24;
export const ESP32C3_SPI_MISO_DLEN_OFFS = 0x28;
export const ESP32C3_SPI_W0_OFFS = 0x58;
export const ESP32C3_UART_DATE_REG_ADDR = 0x6000007c;
export const ESP32C3_BOOTLOADER_FLASH_OFFSET = 0x0000;
// ESP32-C3 RTC Watchdog Timer registers
export const ESP32C3_RTC_CNTL_BASE_REG = 0x60008000;
export const ESP32C3_RTC_CNTL_WDTWPROTECT_REG =
  ESP32C3_RTC_CNTL_BASE_REG + 0x00a8;
export const ESP32C3_RTC_CNTL_WDTCONFIG0_REG =
  ESP32C3_RTC_CNTL_BASE_REG + 0x0090;
export const ESP32C3_RTC_CNTL_WDTCONFIG1_REG =
  ESP32C3_RTC_CNTL_BASE_REG + 0x0094;
export const ESP32C3_RTC_CNTL_WDT_WKEY = 0x50d83aa1;
export const ESP32C3_RTC_CNTL_SWD_WKEY = 0x8f1d312a;
export const ESP32C3_RTC_CNTL_SWD_CONF_REG = ESP32C3_RTC_CNTL_BASE_REG + 0x00ac;
export const ESP32C3_RTC_CNTL_SWD_AUTO_FEED_EN = 1 << 31;
export const ESP32C3_RTC_CNTL_SWD_WPROTECT_REG =
  ESP32C3_RTC_CNTL_BASE_REG + 0x00b0;
export const ESP32C3_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3; // The above var when USB-JTAG/Serial is used
export const ESP32C3_BUF_UART_NO_OFFSET = 24;
// Note: ESP32C3_BSS_UART_DEV_ADDR is calculated dynamically based on chip revision in esp_loader.ts
// Revision < 101: 0x3FCDF064, Revision >= 101: 0x3FCDF060
// ESP32-C3 EFUSE registers for chip revision detection
export const ESP32C3_EFUSE_RD_MAC_SPI_SYS_3_REG = 0x60008850;
export const ESP32C3_EFUSE_RD_MAC_SPI_SYS_5_REG = 0x60008858;

export const ESP32C5_SPI_REG_BASE = 0x60003000;
export const ESP32C5_BASEFUSEADDR = 0x600b4800;
export const ESP32C5_EFUSE_BLOCK1_ADDR = ESP32C5_BASEFUSEADDR + 0x044;
export const ESP32C5_MACFUSEADDR = 0x600b4800 + 0x044;
export const ESP32C5_SPI_USR_OFFS = 0x18;
export const ESP32C5_SPI_USR1_OFFS = 0x1c;
export const ESP32C5_SPI_USR2_OFFS = 0x20;
export const ESP32C5_SPI_MOSI_DLEN_OFFS = 0x24;
export const ESP32C5_SPI_MISO_DLEN_OFFS = 0x28;
export const ESP32C5_SPI_W0_OFFS = 0x58;
export const ESP32C5_UART_DATE_REG_ADDR = 0x6000007c;
export const ESP32C5_UART_CLKDIV_REG = 0x60000014;
export const ESP32C5_BOOTLOADER_FLASH_OFFSET = 0x2000;
// ESP32-C5 Crystal frequency detection registers
export const ESP32C5_PCR_SYSCLK_CONF_REG = 0x60096110;
export const ESP32C5_PCR_SYSCLK_XTAL_FREQ_V = 0x7f << 24;
export const ESP32C5_PCR_SYSCLK_XTAL_FREQ_S = 24;
// ESP32-C5 USB-JTAG/Serial detection
export const ESP32C5_UARTDEV_BUF_NO = 0x4085f514; // Variable in ROM .bss which indicates the port in use
export const ESP32C5_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3; // The above var when USB-JTAG/Serial is used

export const ESP32C6_SPI_REG_BASE = 0x60003000;
export const ESP32C6_BASEFUSEADDR = 0x600b0800;
export const ESP32C6_EFUSE_BLOCK1_ADDR = ESP32C6_BASEFUSEADDR + 0x044;
export const ESP32C6_MACFUSEADDR = 0x600b0800 + 0x044;
export const ESP32C6_SPI_USR_OFFS = 0x18;
export const ESP32C6_SPI_USR1_OFFS = 0x1c;
export const ESP32C6_SPI_USR2_OFFS = 0x20;
export const ESP32C6_SPI_MOSI_DLEN_OFFS = 0x24;
export const ESP32C6_SPI_MISO_DLEN_OFFS = 0x28;
export const ESP32C6_SPI_W0_OFFS = 0x58;
export const ESP32C6_UART_DATE_REG_ADDR = 0x6000007c;
export const ESP32C6_BOOTLOADER_FLASH_OFFSET = 0x0000;
// ESP32-C6 RTC Watchdog Timer registers (LP_WDT)
export const ESP32C6_DR_REG_LP_WDT_BASE = 0x600b1c00;
export const ESP32C6_RTC_CNTL_WDTWPROTECT_REG =
  ESP32C6_DR_REG_LP_WDT_BASE + 0x0018; // LP_WDT_RWDT_WPROTECT_REG
export const ESP32C6_RTC_CNTL_WDTCONFIG0_REG =
  ESP32C6_DR_REG_LP_WDT_BASE + 0x0000; // LP_WDT_RWDT_CONFIG0_REG
export const ESP32C6_RTC_CNTL_WDTCONFIG1_REG =
  ESP32C6_DR_REG_LP_WDT_BASE + 0x0004; // LP_WDT_RWDT_CONFIG1_REG
export const ESP32C6_RTC_CNTL_WDT_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY, same as WDT key in this case
export const ESP32C6_RTC_CNTL_SWD_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY, same as WDT key in this case
// ESP32-C6 USB-JTAG/Serial detection
export const ESP32C6_UARTDEV_BUF_NO = 0x4087f580; // Variable in ROM .bss which indicates the port in use
export const ESP32C6_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3; // The above var when USB-JTAG/Serial is used

// ESP32-C5/C6 LP Watchdog Timer registers (Low Power WDT)
export const ESP32C5_C6_DR_REG_LP_WDT_BASE = 0x600b1c00;
export const ESP32C5_C6_RTC_CNTL_WDTCONFIG0_REG =
  ESP32C5_C6_DR_REG_LP_WDT_BASE + 0x0000; // LP_WDT_RWDT_CONFIG0_REG
export const ESP32C5_C6_RTC_CNTL_WDTCONFIG1_REG =
  ESP32C5_C6_DR_REG_LP_WDT_BASE + 0x0004; // LP_WDT_RWDT_CONFIG1_REG
export const ESP32C5_C6_RTC_CNTL_WDTWPROTECT_REG =
  ESP32C5_C6_DR_REG_LP_WDT_BASE + 0x0018; // LP_WDT_RWDT_WPROTECT_REG
export const ESP32C5_C6_RTC_CNTL_WDT_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY
export const ESP32C5_C6_RTC_CNTL_SWD_CONF_REG =
  ESP32C5_C6_DR_REG_LP_WDT_BASE + 0x001c; // LP_WDT_SWD_CONFIG_REG
export const ESP32C5_C6_RTC_CNTL_SWD_AUTO_FEED_EN = 1 << 18;
export const ESP32C5_C6_RTC_CNTL_SWD_WPROTECT_REG =
  ESP32C5_C6_DR_REG_LP_WDT_BASE + 0x0020; // LP_WDT_SWD_WPROTECT_REG

export const ESP32C61_SPI_REG_BASE = 0x60003000;
export const ESP32C61_BASEFUSEADDR = 0x600b4800;
export const ESP32C61_EFUSE_BLOCK1_ADDR = ESP32C61_BASEFUSEADDR + 0x044;
export const ESP32C61_MACFUSEADDR = 0x600b4800 + 0x044;
export const ESP32C61_SPI_USR_OFFS = 0x18;
export const ESP32C61_SPI_USR1_OFFS = 0x1c;
export const ESP32C61_SPI_USR2_OFFS = 0x20;
export const ESP32C61_SPI_MOSI_DLEN_OFFS = 0x24;
export const ESP32C61_SPI_MISO_DLEN_OFFS = 0x28;
export const ESP32C61_SPI_W0_OFFS = 0x58;
export const ESP32C61_UART_DATE_REG_ADDR = 0x6000007c;
export const ESP32C61_BOOTLOADER_FLASH_OFFSET = 0x0000;
// ESP32-C61 USB-JTAG/Serial detection (dynamic based on chip revision)
export const ESP32C61_UARTDEV_BUF_NO_REV_LE2 = 0x4084f5ec; // revision <= 2
export const ESP32C61_UARTDEV_BUF_NO_REV_GT2 = 0x4084f5e4; // revision > 2
export const ESP32C61_UARTDEV_BUF_NO_USB_JTAG_SERIAL_REV_LE2 = 3; // revision <= 2
export const ESP32C61_UARTDEV_BUF_NO_USB_JTAG_SERIAL_REV_GT2 = 4; // revision > 2

export const ESP32H2_SPI_REG_BASE = 0x60003000;
export const ESP32H2_BASEFUSEADDR = 0x600b0800;
export const ESP32H2_EFUSE_BLOCK1_ADDR = ESP32H2_BASEFUSEADDR + 0x044;
export const ESP32H2_MACFUSEADDR = 0x600b0800 + 0x044;
export const ESP32H2_SPI_USR_OFFS = 0x18;
export const ESP32H2_SPI_USR1_OFFS = 0x1c;
export const ESP32H2_SPI_USR2_OFFS = 0x20;
export const ESP32H2_SPI_MOSI_DLEN_OFFS = 0x24;
export const ESP32H2_SPI_MISO_DLEN_OFFS = 0x28;
export const ESP32H2_SPI_W0_OFFS = 0x58;
export const ESP32H2_UART_DATE_REG_ADDR = 0x6000007c;
export const ESP32H2_BOOTLOADER_FLASH_OFFSET = 0x0000;
// ESP32-H2 RTC Watchdog Timer registers (LP_WDT)
export const ESP32H2_DR_REG_LP_WDT_BASE = 0x600b1c00;
export const ESP32H2_RTC_CNTL_WDTWPROTECT_REG =
  ESP32H2_DR_REG_LP_WDT_BASE + 0x001c; // LP_WDT_RWDT_WPROTECT_REG
export const ESP32H2_RTC_CNTL_WDTCONFIG0_REG =
  ESP32H2_DR_REG_LP_WDT_BASE + 0x0000; // LP_WDT_RWDT_CONFIG0_REG
export const ESP32H2_RTC_CNTL_WDTCONFIG1_REG =
  ESP32H2_DR_REG_LP_WDT_BASE + 0x0004; // LP_WDT_RWDT_CONFIG1_REG
export const ESP32H2_RTC_CNTL_WDT_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY, same as WDT key in this case
export const ESP32H2_RTC_CNTL_SWD_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY, same as WDT key in this case
// ESP32-H2 USB-JTAG/Serial detection
export const ESP32H2_UARTDEV_BUF_NO = 0x4084fefc; // Variable in ROM .bss which indicates the port in use
export const ESP32H2_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3; // The above var when USB-JTAG/Serial is used

export const ESP32H4_SPI_REG_BASE = 0x60099000;
export const ESP32H4_BASEFUSEADDR = 0x600b1800;
export const ESP32H4_EFUSE_BLOCK1_ADDR = ESP32H4_BASEFUSEADDR + 0x044;
export const ESP32H4_MACFUSEADDR = 0x600b1800 + 0x044;
export const ESP32H4_SPI_USR_OFFS = 0x18;
export const ESP32H4_SPI_USR1_OFFS = 0x1c;
export const ESP32H4_SPI_USR2_OFFS = 0x20;
export const ESP32H4_SPI_MOSI_DLEN_OFFS = 0x24;
export const ESP32H4_SPI_MISO_DLEN_OFFS = 0x28;
export const ESP32H4_SPI_W0_OFFS = 0x58;
export const ESP32H4_UART_DATE_REG_ADDR = 0x60012000 + 0x7c;
export const ESP32H4_BOOTLOADER_FLASH_OFFSET = 0x2000;
// ESP32-H4 RTC Watchdog Timer registers
export const ESP32H4_DR_REG_LP_WDT_BASE = 0x600b5400;
export const ESP32H4_RTC_CNTL_WDTWPROTECT_REG =
  ESP32H4_DR_REG_LP_WDT_BASE + 0x0018; // LP_WDT_RWDT_WPROTECT_REG
export const ESP32H4_RTC_CNTL_WDTCONFIG0_REG =
  ESP32H4_DR_REG_LP_WDT_BASE + 0x0000; // LP_WDT_RWDT_CONFIG0_REG
export const ESP32H4_RTC_CNTL_WDTCONFIG1_REG =
  ESP32H4_DR_REG_LP_WDT_BASE + 0x0004; // LP_WDT_RWDT_CONFIG1_REG
export const ESP32H4_RTC_CNTL_WDT_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY, same as WDT key in this case
export const ESP32H4_RTC_CNTL_SWD_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY, same as WDT key in this case
// ESP32-H4 USB-JTAG/Serial detection
export const ESP32H4_UARTDEV_BUF_NO = 0x4087f580; // Variable in ROM .bss which indicates the port in use
export const ESP32H4_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3; // The above var when USB-JTAG/Serial is used

export const ESP32H21_SPI_REG_BASE = 0x60003000;
export const ESP32H21_BASEFUSEADDR = 0x600b4000;
export const ESP32H21_EFUSE_BLOCK1_ADDR = ESP32H21_BASEFUSEADDR + 0x044;
export const ESP32H21_MACFUSEADDR = 0x600b4000 + 0x044;
export const ESP32H21_SPI_USR_OFFS = 0x18;
export const ESP32H21_SPI_USR1_OFFS = 0x1c;
export const ESP32H21_SPI_USR2_OFFS = 0x20;
export const ESP32H21_SPI_MOSI_DLEN_OFFS = 0x24;
export const ESP32H21_SPI_MISO_DLEN_OFFS = 0x28;
export const ESP32H21_SPI_W0_OFFS = 0x58;
export const ESP32H21_UART_DATE_REG_ADDR = 0x6000007c;
export const ESP32H21_BOOTLOADER_FLASH_OFFSET = 0x0000;
// ESP32-H21 RTC Watchdog Timer registers (LP_WDT)
export const ESP32H21_DR_REG_LP_WDT_BASE = 0x600b1c00;
export const ESP32H21_RTC_CNTL_WDTWPROTECT_REG =
  ESP32H21_DR_REG_LP_WDT_BASE + 0x001c;
export const ESP32H21_RTC_CNTL_WDTCONFIG0_REG =
  ESP32H21_DR_REG_LP_WDT_BASE + 0x0000;
export const ESP32H21_RTC_CNTL_WDTCONFIG1_REG =
  ESP32H21_DR_REG_LP_WDT_BASE + 0x0004; // LP_WDT_RWDT_CONFIG1_REG
export const ESP32H21_RTC_CNTL_WDT_WKEY = 0x50d83aa1;
export const ESP32H21_RTC_CNTL_SWD_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY, same as WDT key in this case

export const ESP32P4_SPI_REG_BASE = 0x5008d000;
export const ESP32P4_BASEFUSEADDR = 0x5012d000;
export const ESP32P4_EFUSE_BLOCK1_ADDR = ESP32P4_BASEFUSEADDR + 0x044;
export const ESP32P4_MACFUSEADDR = 0x5012d000 + 0x044;
export const ESP32P4_SPI_USR_OFFS = 0x18;
export const ESP32P4_SPI_USR1_OFFS = 0x1c;
export const ESP32P4_SPI_USR2_OFFS = 0x20;
export const ESP32P4_SPI_MOSI_DLEN_OFFS = 0x24;
export const ESP32P4_SPI_MISO_DLEN_OFFS = 0x28;
export const ESP32P4_SPI_W0_OFFS = 0x58;
export const ESP32P4_UART_DATE_REG_ADDR = 0x500ca000 + 0x8c;
export const ESP32P4_BOOTLOADER_FLASH_OFFSET = 0x2000;
// ESP32-P4 RTC Watchdog Timer registers
export const ESP32P4_DR_REG_LP_WDT_BASE = 0x50116000;
export const ESP32P4_RTC_CNTL_WDTWPROTECT_REG =
  ESP32P4_DR_REG_LP_WDT_BASE + 0x0018; // LP_WDT_WPROTECT_REG
export const ESP32P4_RTC_CNTL_WDTCONFIG0_REG =
  ESP32P4_DR_REG_LP_WDT_BASE + 0x0000; // LP_WDT_CONFIG0_REG
export const ESP32P4_RTC_CNTL_WDTCONFIG1_REG =
  ESP32P4_DR_REG_LP_WDT_BASE + 0x0004; // LP_WDT_CONFIG1_REG
export const ESP32P4_RTC_CNTL_WDT_WKEY = 0x50d83aa1;
export const ESP32P4_RTC_CNTL_SWD_CONF_REG =
  ESP32P4_DR_REG_LP_WDT_BASE + 0x001c; // RTC_WDT_SWD_CONFIG_REG
export const ESP32P4_RTC_CNTL_SWD_AUTO_FEED_EN = 1 << 18;
export const ESP32P4_RTC_CNTL_SWD_WPROTECT_REG =
  ESP32P4_DR_REG_LP_WDT_BASE + 0x0020; // RTC_WDT_SWD_WPROTECT_REG
export const ESP32P4_RTC_CNTL_SWD_WKEY = 0x50d83aa1; // RTC_WDT_SWD_WKEY, same as WDT key in this case
// ESP32-P4 USB-JTAG/Serial and USB-OTG detection
// Note: UARTDEV_BUF_NO is dynamic based on chip revision
// Revision < 300: 0x4FF3FEB0 + 24 = 0x4FF3FEC8
// Revision >= 300: 0x4FFBFEB0 + 24 = 0x4FFBFEC8
export const ESP32P4_UARTDEV_BUF_NO_REV0 = 0x4ff3fec8; // Variable in ROM .bss (revision < 300)
export const ESP32P4_UARTDEV_BUF_NO_REV300 = 0x4ffbfec8; // Variable in ROM .bss (revision >= 300)
export const ESP32P4_UARTDEV_BUF_NO_USB_OTG = 5; // The above var when USB-OTG is used
export const ESP32P4_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 6; // The above var when USB-JTAG/Serial is used
export const ESP32P4_GPIO_STRAP_REG = 0x500e0038;
export const ESP32P4_GPIO_STRAP_SPI_BOOT_MASK = 0x8; // Not download mode
export const ESP32P4_RTC_CNTL_OPTION1_REG = 0x50110008;
export const ESP32P4_RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK = 0x4; // Is download mode forced over USB?

// Flash power-on related registers and bits needed for ECO6 (Rev 301)
export const ESP32P4_DR_REG_LPAON_BASE = 0x50110000;
export const ESP32P4_DR_REG_PMU_BASE = ESP32P4_DR_REG_LPAON_BASE + 0x5000;
export const ESP32P4_DR_REG_LP_SYS_BASE = ESP32P4_DR_REG_LPAON_BASE + 0x0;
export const ESP32P4_LP_SYSTEM_REG_ANA_XPD_PAD_GROUP_REG =
  ESP32P4_DR_REG_LP_SYS_BASE + 0x10c;
export const ESP32P4_PMU_EXT_LDO_P0_0P1A_ANA_REG =
  ESP32P4_DR_REG_PMU_BASE + 0x1bc;
export const ESP32P4_PMU_ANA_0P1A_EN_CUR_LIM_0 = 1 << 27;
export const ESP32P4_PMU_EXT_LDO_P0_0P1A_REG = ESP32P4_DR_REG_PMU_BASE + 0x1b8;
export const ESP32P4_PMU_0P1A_TARGET0_0 = 0xff << 23;
export const ESP32P4_PMU_0P1A_FORCE_TIEH_SEL_0 = 1 << 7;
export const ESP32P4_PMU_DATE_REG = ESP32P4_DR_REG_PMU_BASE + 0x3fc;

export const ESP32S31_SPI_REG_BASE = 0x20501000;
export const ESP32S31_BASEFUSEADDR = 0x20715000;
export const ESP32S31_EFUSE_BLOCK1_ADDR = ESP32S31_BASEFUSEADDR + 0x050;
export const ESP32S31_MACFUSEADDR = ESP32S31_BASEFUSEADDR + 0x050;
export const ESP32S31_SPI_USR_OFFS = 0x18;
export const ESP32S31_SPI_USR1_OFFS = 0x1c;
export const ESP32S31_SPI_USR2_OFFS = 0x20;
export const ESP32S31_SPI_MOSI_DLEN_OFFS = 0x24;
export const ESP32S31_SPI_MISO_DLEN_OFFS = 0x28;
export const ESP32S31_SPI_W0_OFFS = 0x58;
export const ESP32S31_UART_DATE_REG_ADDR = 0x2038a000 + 0x8c;
export const ESP32S31_BOOTLOADER_FLASH_OFFSET = 0x2000;
// ESP32-S31 RTC Watchdog Timer registers (LP_WDT)
export const ESP32S31_DR_REG_LP_WDT_BASE = 0x20801000;
export const ESP32S31_RTC_CNTL_WDTCONFIG0_REG =
  ESP32S31_DR_REG_LP_WDT_BASE + 0x0000; // LP_WDT_RWDT_CONFIG0_REG
export const ESP32S31_RTC_CNTL_WDTCONFIG1_REG =
  ESP32S31_DR_REG_LP_WDT_BASE + 0x0004; // LP_WDT_RWDT_CONFIG1_REG
export const ESP32S31_RTC_CNTL_WDTWPROTECT_REG =
  ESP32S31_DR_REG_LP_WDT_BASE + 0x0018; // LP_WDT_RWDT_WPROTECT_REG
export const ESP32S31_RTC_CNTL_WDT_WKEY = 0x50d83aa1;

export interface SpiFlashAddresses {
  regBase: number;
  baseFuse: number;
  macFuse: number;
  usrOffs: number;
  usr1Offs: number;
  usr2Offs: number;
  mosiDlenOffs: number;
  misoDlenOffs: number;
  w0Offs: number;
  uartDateReg: number;
  flashOffs: number;
}

export const SYNC_PACKET = toByteArray(
  "\x07\x07\x12 UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU",
);
export const CHIP_DETECT_MAGIC_REG_ADDR = 0x40001000;

// Image Chip IDs (used by ESP32-C3 and later for chip detection)
// These values for the families are made up; nothing that esptool uses.
export const CHIP_FAMILY_ESP8266 = 0x8266;
export const CHIP_FAMILY_ESP32 = 0x32;
export const CHIP_FAMILY_ESP32S2 = 0x3252;
export const CHIP_FAMILY_ESP32S3 = 0x3253;
export const CHIP_FAMILY_ESP32C2 = 0x32c2;
export const CHIP_FAMILY_ESP32C3 = 0x32c3;
export const CHIP_FAMILY_ESP32C5 = 0x32c5;
export const CHIP_FAMILY_ESP32C6 = 0x32c6;
export const CHIP_FAMILY_ESP32C61 = 0x32c61;
export const CHIP_FAMILY_ESP32H2 = 0x3272;
export const CHIP_FAMILY_ESP32H4 = 0x3274;
export const CHIP_FAMILY_ESP32H21 = 0x3275;
export const CHIP_FAMILY_ESP32P4 = 0x3280;
export const CHIP_FAMILY_ESP32S31 = 0x3231;
export type ChipFamily =
  | typeof CHIP_FAMILY_ESP8266
  | typeof CHIP_FAMILY_ESP32
  | typeof CHIP_FAMILY_ESP32S2
  | typeof CHIP_FAMILY_ESP32S3
  | typeof CHIP_FAMILY_ESP32C2
  | typeof CHIP_FAMILY_ESP32C3
  | typeof CHIP_FAMILY_ESP32C5
  | typeof CHIP_FAMILY_ESP32C6
  | typeof CHIP_FAMILY_ESP32C61
  | typeof CHIP_FAMILY_ESP32H2
  | typeof CHIP_FAMILY_ESP32H4
  | typeof CHIP_FAMILY_ESP32H21
  | typeof CHIP_FAMILY_ESP32P4
  | typeof CHIP_FAMILY_ESP32S31;

interface ChipIdInfo {
  name: string;
  family: ChipFamily;
}

export const CHIP_ID_TO_INFO: { [chipId: number]: ChipIdInfo } = {
  5: { name: "ESP32-C3", family: CHIP_FAMILY_ESP32C3 },
  9: { name: "ESP32-S3", family: CHIP_FAMILY_ESP32S3 },
  12: { name: "ESP32-C2", family: CHIP_FAMILY_ESP32C2 },
  13: { name: "ESP32-C6", family: CHIP_FAMILY_ESP32C6 },
  16: { name: "ESP32-H2", family: CHIP_FAMILY_ESP32H2 },
  18: { name: "ESP32-P4", family: CHIP_FAMILY_ESP32P4 },
  20: { name: "ESP32-C61", family: CHIP_FAMILY_ESP32C61 },
  23: { name: "ESP32-C5", family: CHIP_FAMILY_ESP32C5 },
  25: { name: "ESP32-H21", family: CHIP_FAMILY_ESP32H21 },
  28: { name: "ESP32-H4", family: CHIP_FAMILY_ESP32H4 },
  32: { name: "ESP32-S31", family: CHIP_FAMILY_ESP32S31 },
};

interface ChipInfo {
  [magicValue: number]: {
    name: string;
    family: ChipFamily;
  };
}

export const CHIP_DETECT_MAGIC_VALUES: ChipInfo = {
  0xfff0c101: { name: "ESP8266", family: CHIP_FAMILY_ESP8266 },
  0x00f01d83: { name: "ESP32", family: CHIP_FAMILY_ESP32 },
  0x000007c6: { name: "ESP32-S2", family: CHIP_FAMILY_ESP32S2 },
};

// Commands supported by ESP8266 ROM bootloader
export const ESP_FLASH_BEGIN = 0x02;
export const ESP_FLASH_DATA = 0x03;
export const ESP_FLASH_END = 0x04;
export const ESP_MEM_BEGIN = 0x05;
export const ESP_MEM_END = 0x06;
export const ESP_MEM_DATA = 0x07;
export const ESP_SYNC = 0x08;
export const ESP_WRITE_REG = 0x09;
export const ESP_READ_REG = 0x0a;

export const ESP_ERASE_FLASH = 0xd0;
export const ESP_ERASE_REGION = 0xd1;
export const ESP_READ_FLASH = 0xd2;

export const ESP_SPI_SET_PARAMS = 0x0b;
export const ESP_SPI_ATTACH = 0x0d;
export const ESP_CHANGE_BAUDRATE = 0x0f;
export const ESP_SPI_FLASH_MD5 = 0x13;
export const ESP_GET_SECURITY_INFO = 0x14;
export const ESP_CHECKSUM_MAGIC = 0xef;
export const ESP_FLASH_DEFL_BEGIN = 0x10;
export const ESP_FLASH_DEFL_DATA = 0x11;
export const ESP_FLASH_DEFL_END = 0x12;

export const ROM_INVALID_RECV_MSG = 0x05;

export const USB_RAM_BLOCK = 0x800;
export const ESP_RAM_BLOCK = 0x1800;

// Timeouts
export const DEFAULT_TIMEOUT = 3000;
export const CHIP_ERASE_TIMEOUT = 150000; // timeout for full chip erase in ms
export const MAX_TIMEOUT = CHIP_ERASE_TIMEOUT * 2; // longest any command can run in ms
export const SYNC_TIMEOUT = 100; // timeout for syncing with bootloader in ms
export const ERASE_REGION_TIMEOUT_PER_MB = 30000; // timeout (per megabyte) for erasing a region in ms
export const MEM_END_ROM_TIMEOUT = 500;
export const FLASH_READ_TIMEOUT = 100; // timeout for reading flash in ms

/**
 * @name timeoutPerMb
 * Scales timeouts which are size-specific
 */
export const timeoutPerMb = (secondsPerMb: number, sizeBytes: number) => {
  const result = Math.floor(secondsPerMb * (sizeBytes / 0x1e6));
  if (result < DEFAULT_TIMEOUT) {
    return DEFAULT_TIMEOUT;
  }
  return result;
};

export const getSpiFlashAddresses = (
  chipFamily: ChipFamily,
): SpiFlashAddresses => {
  switch (chipFamily) {
    case CHIP_FAMILY_ESP32:
      return {
        regBase: ESP32_SPI_REG_BASE,
        baseFuse: ESP32_BASEFUSEADDR,
        macFuse: ESP32_MACFUSEADDR,
        usrOffs: ESP32_SPI_USR_OFFS,
        usr1Offs: ESP32_SPI_USR1_OFFS,
        usr2Offs: ESP32_SPI_USR2_OFFS,
        mosiDlenOffs: ESP32_SPI_MOSI_DLEN_OFFS,
        misoDlenOffs: ESP32_SPI_MISO_DLEN_OFFS,
        w0Offs: ESP32_SPI_W0_OFFS,
        uartDateReg: ESP32_UART_DATE_REG_ADDR,
        flashOffs: ESP32_BOOTLOADER_FLASH_OFFSET,
      };
    case CHIP_FAMILY_ESP32S2:
      return {
        regBase: ESP32S2_SPI_REG_BASE,
        baseFuse: ESP32S2_BASEFUSEADDR,
        macFuse: ESP32S2_MACFUSEADDR,
        usrOffs: ESP32S2_SPI_USR_OFFS,
        usr1Offs: ESP32S2_SPI_USR1_OFFS,
        usr2Offs: ESP32S2_SPI_USR2_OFFS,
        mosiDlenOffs: ESP32S2_SPI_MOSI_DLEN_OFFS,
        misoDlenOffs: ESP32S2_SPI_MISO_DLEN_OFFS,
        w0Offs: ESP32S2_SPI_W0_OFFS,
        uartDateReg: ESP32S2_UART_DATE_REG_ADDR,
        flashOffs: ESP32S2_BOOTLOADER_FLASH_OFFSET,
      };
    case CHIP_FAMILY_ESP32S3:
      return {
        regBase: ESP32S3_SPI_REG_BASE,
        usrOffs: ESP32S3_SPI_USR_OFFS,
        baseFuse: ESP32S3_BASEFUSEADDR,
        macFuse: ESP32S3_MACFUSEADDR,
        usr1Offs: ESP32S3_SPI_USR1_OFFS,
        usr2Offs: ESP32S3_SPI_USR2_OFFS,
        mosiDlenOffs: ESP32S3_SPI_MOSI_DLEN_OFFS,
        misoDlenOffs: ESP32S3_SPI_MISO_DLEN_OFFS,
        w0Offs: ESP32S3_SPI_W0_OFFS,
        uartDateReg: ESP32S3_UART_DATE_REG_ADDR,
        flashOffs: ESP32S3_BOOTLOADER_FLASH_OFFSET,
      };
    case CHIP_FAMILY_ESP8266:
      return {
        regBase: ESP8266_SPI_REG_BASE,
        usrOffs: ESP8266_SPI_USR_OFFS,
        baseFuse: ESP8266_BASEFUSEADDR,
        macFuse: ESP8266_MACFUSEADDR,
        usr1Offs: ESP8266_SPI_USR1_OFFS,
        usr2Offs: ESP8266_SPI_USR2_OFFS,
        mosiDlenOffs: ESP8266_SPI_MOSI_DLEN_OFFS,
        misoDlenOffs: ESP8266_SPI_MISO_DLEN_OFFS,
        w0Offs: ESP8266_SPI_W0_OFFS,
        uartDateReg: ESP8266_UART_DATE_REG_ADDR,
        flashOffs: ESP8266_BOOTLOADER_FLASH_OFFSET,
      };
    case CHIP_FAMILY_ESP32C2:
      return {
        regBase: ESP32C2_SPI_REG_BASE,
        baseFuse: ESP32C2_BASEFUSEADDR,
        macFuse: ESP32C2_MACFUSEADDR,
        usrOffs: ESP32C2_SPI_USR_OFFS,
        usr1Offs: ESP32C2_SPI_USR1_OFFS,
        usr2Offs: ESP32C2_SPI_USR2_OFFS,
        mosiDlenOffs: ESP32C2_SPI_MOSI_DLEN_OFFS,
        misoDlenOffs: ESP32C2_SPI_MISO_DLEN_OFFS,
        w0Offs: ESP32C2_SPI_W0_OFFS,
        uartDateReg: ESP32C2_UART_DATE_REG_ADDR,
        flashOffs: ESP32C2_BOOTLOADER_FLASH_OFFSET,
      };
    case CHIP_FAMILY_ESP32C3:
      return {
        regBase: ESP32C3_SPI_REG_BASE,
        baseFuse: ESP32C3_BASEFUSEADDR,
        macFuse: ESP32C3_MACFUSEADDR,
        usrOffs: ESP32C3_SPI_USR_OFFS,
        usr1Offs: ESP32C3_SPI_USR1_OFFS,
        usr2Offs: ESP32C3_SPI_USR2_OFFS,
        mosiDlenOffs: ESP32C3_SPI_MOSI_DLEN_OFFS,
        misoDlenOffs: ESP32C3_SPI_MISO_DLEN_OFFS,
        w0Offs: ESP32C3_SPI_W0_OFFS,
        uartDateReg: ESP32C3_UART_DATE_REG_ADDR,
        flashOffs: ESP32C3_BOOTLOADER_FLASH_OFFSET,
      };
    case CHIP_FAMILY_ESP32C5:
      return {
        regBase: ESP32C5_SPI_REG_BASE,
        baseFuse: ESP32C5_BASEFUSEADDR,
        macFuse: ESP32C5_MACFUSEADDR,
        usrOffs: ESP32C5_SPI_USR_OFFS,
        usr1Offs: ESP32C5_SPI_USR1_OFFS,
        usr2Offs: ESP32C5_SPI_USR2_OFFS,
        mosiDlenOffs: ESP32C5_SPI_MOSI_DLEN_OFFS,
        misoDlenOffs: ESP32C5_SPI_MISO_DLEN_OFFS,
        w0Offs: ESP32C5_SPI_W0_OFFS,
        uartDateReg: ESP32C5_UART_DATE_REG_ADDR,
        flashOffs: ESP32C5_BOOTLOADER_FLASH_OFFSET,
      };
    case CHIP_FAMILY_ESP32C6:
      return {
        regBase: ESP32C6_SPI_REG_BASE,
        baseFuse: ESP32C6_BASEFUSEADDR,
        macFuse: ESP32C6_MACFUSEADDR,
        usrOffs: ESP32C6_SPI_USR_OFFS,
        usr1Offs: ESP32C6_SPI_USR1_OFFS,
        usr2Offs: ESP32C6_SPI_USR2_OFFS,
        mosiDlenOffs: ESP32C6_SPI_MOSI_DLEN_OFFS,
        misoDlenOffs: ESP32C6_SPI_MISO_DLEN_OFFS,
        w0Offs: ESP32C6_SPI_W0_OFFS,
        uartDateReg: ESP32C6_UART_DATE_REG_ADDR,
        flashOffs: ESP32C6_BOOTLOADER_FLASH_OFFSET,
      };
    case CHIP_FAMILY_ESP32C61:
      return {
        regBase: ESP32C61_SPI_REG_BASE,
        baseFuse: ESP32C61_BASEFUSEADDR,
        macFuse: ESP32C61_MACFUSEADDR,
        usrOffs: ESP32C61_SPI_USR_OFFS,
        usr1Offs: ESP32C61_SPI_USR1_OFFS,
        usr2Offs: ESP32C61_SPI_USR2_OFFS,
        mosiDlenOffs: ESP32C61_SPI_MOSI_DLEN_OFFS,
        misoDlenOffs: ESP32C61_SPI_MISO_DLEN_OFFS,
        w0Offs: ESP32C61_SPI_W0_OFFS,
        uartDateReg: ESP32C61_UART_DATE_REG_ADDR,
        flashOffs: ESP32C61_BOOTLOADER_FLASH_OFFSET,
      };
    case CHIP_FAMILY_ESP32H2:
      return {
        regBase: ESP32H2_SPI_REG_BASE,
        baseFuse: ESP32H2_BASEFUSEADDR,
        macFuse: ESP32H2_MACFUSEADDR,
        usrOffs: ESP32H2_SPI_USR_OFFS,
        usr1Offs: ESP32H2_SPI_USR1_OFFS,
        usr2Offs: ESP32H2_SPI_USR2_OFFS,
        mosiDlenOffs: ESP32H2_SPI_MOSI_DLEN_OFFS,
        misoDlenOffs: ESP32H2_SPI_MISO_DLEN_OFFS,
        w0Offs: ESP32H2_SPI_W0_OFFS,
        uartDateReg: ESP32H2_UART_DATE_REG_ADDR,
        flashOffs: ESP32H2_BOOTLOADER_FLASH_OFFSET,
      };
    case CHIP_FAMILY_ESP32H4:
      return {
        regBase: ESP32H4_SPI_REG_BASE,
        baseFuse: ESP32H4_BASEFUSEADDR,
        macFuse: ESP32H4_MACFUSEADDR,
        usrOffs: ESP32H4_SPI_USR_OFFS,
        usr1Offs: ESP32H4_SPI_USR1_OFFS,
        usr2Offs: ESP32H4_SPI_USR2_OFFS,
        mosiDlenOffs: ESP32H4_SPI_MOSI_DLEN_OFFS,
        misoDlenOffs: ESP32H4_SPI_MISO_DLEN_OFFS,
        w0Offs: ESP32H4_SPI_W0_OFFS,
        uartDateReg: ESP32H4_UART_DATE_REG_ADDR,
        flashOffs: ESP32H4_BOOTLOADER_FLASH_OFFSET,
      };
    case CHIP_FAMILY_ESP32H21:
      return {
        regBase: ESP32H21_SPI_REG_BASE,
        baseFuse: ESP32H21_BASEFUSEADDR,
        macFuse: ESP32H21_MACFUSEADDR,
        usrOffs: ESP32H21_SPI_USR_OFFS,
        usr1Offs: ESP32H21_SPI_USR1_OFFS,
        usr2Offs: ESP32H21_SPI_USR2_OFFS,
        mosiDlenOffs: ESP32H21_SPI_MOSI_DLEN_OFFS,
        misoDlenOffs: ESP32H21_SPI_MISO_DLEN_OFFS,
        w0Offs: ESP32H21_SPI_W0_OFFS,
        uartDateReg: ESP32H21_UART_DATE_REG_ADDR,
        flashOffs: ESP32H21_BOOTLOADER_FLASH_OFFSET,
      };
    case CHIP_FAMILY_ESP32P4:
      return {
        regBase: ESP32P4_SPI_REG_BASE,
        baseFuse: ESP32P4_BASEFUSEADDR,
        macFuse: ESP32P4_MACFUSEADDR,
        usrOffs: ESP32P4_SPI_USR_OFFS,
        usr1Offs: ESP32P4_SPI_USR1_OFFS,
        usr2Offs: ESP32P4_SPI_USR2_OFFS,
        mosiDlenOffs: ESP32P4_SPI_MOSI_DLEN_OFFS,
        misoDlenOffs: ESP32P4_SPI_MISO_DLEN_OFFS,
        w0Offs: ESP32P4_SPI_W0_OFFS,
        uartDateReg: ESP32P4_UART_DATE_REG_ADDR,
        flashOffs: ESP32P4_BOOTLOADER_FLASH_OFFSET,
      };
    case CHIP_FAMILY_ESP32S31:
      return {
        regBase: ESP32S31_SPI_REG_BASE,
        baseFuse: ESP32S31_BASEFUSEADDR,
        macFuse: ESP32S31_MACFUSEADDR,
        usrOffs: ESP32S31_SPI_USR_OFFS,
        usr1Offs: ESP32S31_SPI_USR1_OFFS,
        usr2Offs: ESP32S31_SPI_USR2_OFFS,
        mosiDlenOffs: ESP32S31_SPI_MOSI_DLEN_OFFS,
        misoDlenOffs: ESP32S31_SPI_MISO_DLEN_OFFS,
        w0Offs: ESP32S31_SPI_W0_OFFS,
        uartDateReg: ESP32S31_UART_DATE_REG_ADDR,
        flashOffs: ESP32S31_BOOTLOADER_FLASH_OFFSET,
      };
    default:
      return {
        regBase: -1,
        baseFuse: -1,
        macFuse: -1,
        usrOffs: -1,
        usr1Offs: -1,
        usr2Offs: -1,
        mosiDlenOffs: -1,
        misoDlenOffs: -1,
        w0Offs: -1,
        uartDateReg: -1,
        flashOffs: -1,
      };
  }
};

export class SlipReadError extends Error {
  constructor(message: string) {
    super(message);
    this.name = "SlipReadError";
  }
}