; ############################ macro ############################## ; setBank ; ------- ; A -> bit 22-15 of rom address to set in the bank register ; HL <- BANKREG ; ; set the bank register for ROM area ; = 101 cycles macro setBank LD HL, BANKREG ; HL = BANKREG ' 10 LD (HL), A ; #1 (bit 15) ' 7 RRCA ; ' 4 LD (HL), A ; #2 (bit 16) ' 7 RRCA ; ' 4 LD (HL), A ; #3 (bit 17) ' 7 RRCA ; ' 4 LD (HL), A ; #4 (bit 18) ' 7 RRCA ; ' 4 LD (HL), A ; #5 (bit 19) ' 7 RRCA ; ' 4 LD (HL), A ; #6 (bit 20) ' 7 RRCA ; ' 4 LD (HL), A ; #7 (bit 21) ' 7 RRCA ; ' 4 LD (HL), A ; #8 (bit 22) ' 7 LD (HL), L ; #9 (bit 23 = 0) ' 7 endm ; ' 101 ; setBankFast ; ----------- ; A -> bit 21-15 of rom address to set in the bank register ; HL <- BANKREG ; ; set the bank register for ROM area ; = 97 cycles macro setBankFast LD HL, BANKREG ; HL = BANKREG ' 10 LD (HL), A ; #1 (bit 15) ' 7 RRCA ; ' 4 LD (HL), A ; #2 (bit 16) ' 7 RRCA ; ' 4 LD (HL), A ; #3 (bit 17) ' 7 RRCA ; ' 4 LD (HL), A ; #4 (bit 18) ' 7 RRCA ; ' 4 LD (HL), A ; #5 (bit 19) ' 7 RRCA ; ' 4 LD (HL), A ; #6 (bit 20) ' 7 RRCA ; ' 4 LD (HL), A ; #7 (bit 21) ' 7 LD (HL), L ; #8 (bit 22 = 0) ' 7 LD (HL), L ; #9 (bit 23 = 0) ' 7 endm ; ' 97 ; setBank_BC ; ---------- ; A -> bit 21-15 of rom address to set in the bank register ; BC <- BANKREG ; A <- 0 ; ; set the bank register for ROM area ; = 101 cycles macro setBank_BC LD BC, BANKREG ; BC = BANKREG ' 10 LD (BC), A ; #1 (bit 15) ' 7 RRCA ; ' 4 LD (BC), A ; #2 (bit 16) ' 7 RRCA ; ' 4 LD (BC), A ; #3 (bit 17) ' 7 RRCA ; ' 4 LD (BC), A ; #4 (bit 18) ' 7 RRCA ; ' 4 LD (BC), A ; #5 (bit 19) ' 7 RRCA ; ' 4 LD (BC), A ; #6 (bit 20) ' 7 RRCA ; ' 4 LD (BC), A ; #7 (bit 21) ' 7 XOR A ; ' 4 LD (BC), A ; #8 (bit 22 = 0) ' 7 LD (BC), A ; #9 (bit 23 = 0) ' 7 endm ; ' 101 ; setBank_DE ; ---------- ; A -> bit 22-15 of rom address to set in the bank register ; DE <- BANKREG ; A <- 0 ; ; set the bank register for ROM area ; = 105 cycles macro setBank_DE LD DE, BANKREG ; DE = BANKREG ' 10 LD (DE), A ; #1 (bit 15) ' 7 RRCA ; ' 4 LD (DE), A ; #2 (bit 16) ' 7 RRCA ; ' 4 LD (DE), A ; #3 (bit 17) ' 7 RRCA ; ' 4 LD (DE), A ; #4 (bit 18) ' 7 RRCA ; ' 4 LD (DE), A ; #5 (bit 19) ' 7 RRCA ; ' 4 LD (DE), A ; #6 (bit 20) ' 7 RRCA ; ' 4 LD (DE), A ; #7 (bit 21) ' 7 RRCA ; ' 4 LD (DE), A ; #8 (bit 22) ' 7 XOR A ; ' 4 LD (DE), A ; #9 (bit 23 = 0) ' 7 endm ; ' 105 ; writeYMFast ; ----------- ; HL <-> YM port where to write ; D -> address ; E -> value ; ; write to YM2612 (no busy check) ; = 18 cycles macro writeYMFast LD (HL), D ; write address ' 7 | INC L ; next port ' 4 | 18 LD (HL), E ; write value ' 7 | endm ; getPlayCommand ; -------------- ; HL <- point to COMMAND ; zf <- channel 'ch' play command ; ; Z flag reset if play command for channel 'ch' ; = 22 cycles macro getPlayCommand ch LD HL, COMMAND ; ' 10 BIT COMPLAY_SFT+ch, (HL) ; play command ? ' 12 endm ; ' 22 ; getStopCommand ; -------------- ; HL <- point to COMMAND ; zf <- channel 'ch' stop command ; ; Z flag reset if stop command for channel 'ch' ; = 22 cycles macro getStopCommand ch LD HL, COMMAND ; ' 10 BIT COMSTOP_SFT+ch, (HL) ; stop command ? ' 12 endm ; ' 22 ; setPlayCommand ; ---------------- ; HL <- point to COMMAND ; ; set the play command for channel 'ch' ; = 25 cycles macro setPlayCommand ch LD HL, COMMAND ; ' 10 SET COMPLAY_SFT+ch, (HL) ; set command ' 15 endm ; ' 25 ; setStopCommand ; ---------------- ; HL <- point to COMMAND ; ; set the stop command for channel 'ch' ; = 25 cycles macro setStopCommand ch LD HL, COMMAND ; ' 10 SET COMSTOP_SFT+ch, (HL) ; set command ' 15 endm ; ' 25 ; clearPlayCommand ; ---------------- ; HL <- point to COMMAND ; ; clear the play command for channel 'ch' ; = 25 cycles macro clearPlayCommand ch LD HL, COMMAND ; ' 10 RES COMPLAY_SFT+ch, (HL) ; clear command ' 15 endm ; ' 25 ; clearStopCommand ; ---------------- ; HL <- point to COMMAND ; ; clear the stop command for channel 'ch' ; = 25 cycles macro clearStopCommand ch LD HL, COMMAND ; ' 10 RES COMSTOP_SFT+ch, (HL) ; clear command ' 15 endm ; ' 25 ; getPlayStatus ; ------------- ; HL <- point to STATUS ; zf <- channel 'ch' is playing ; ; Z flag reset if play status for channel 'ch' ; = 22 cycles macro getPlayStatus ch LD HL, STATUS ; ' 10 BIT STATPLAY_SFT+ch, (HL) ; get status ' 12 endm ; ' 22 ; setPlayStatus ; ------------- ; HL <- point to STATUS ; ; set the play status for channel 'ch' ; = 25 cycles macro setPlayStatus ch LD HL, STATUS ; ' 10 SET STATPLAY_SFT+ch, (HL) ; set status ' 15 endm ; ' 25 ; clearPlayStatus ; --------------- ; HL <- point to STATUS ; ; clear play status for channel 'ch' ; = 25 cycles macro clearPlayStatus ch LD HL, STATUS ; ' 10 RES STATPLAY_SFT+ch, (HL) ; clear status ' 15 endm ; ' 25 ; getLoopStatus ; ------------- ; HL <- point to STATUS+1 ; zf <- channel 'ch' is playing ; ; Z flag reset if loop status for channel 'ch' ; = 22 cycles macro getLoopStatus ch LD HL, STATUS+1 ; ' 10 BIT STATPLAY_SFT+ch, (HL) ; get status ' 12 endm ; ' 22 ; setLoopStatus ; ------------- ; HL <- point to STATUS+1 ; ; set the loop status for channel 'ch' ; = 25 cycles macro setLoopStatus ch LD HL, STATUS+1 ; ' 10 SET STATPLAY_SFT+ch, (HL) ; set status ' 15 endm ; ' 25 ; clearLoopStatus ; --------------- ; HL <- point to STATUS+1 ; ; clear loop status for channel 'ch' ; = 25 cycles macro clearLoopStatus ch LD HL, STATUS+1 ; ' 10 RES STATPLAY_SFT+ch, (HL) ; clear status ' 15 endm ; ' 25 ; clearAllStatus ; -------------- ; HL <- 0 ; ; clear play and loop status for all channel ; = 26 cycles macro clearAllStatus LD HL, $00 ; ' 10 LD (STATUS), HL ; clear status ' 16 endm ; ' 26 ; ############################ macro wait macro ############################## ; wait2p16x ; --------- ; wait for ((w * 16) + 2) cycles ; macro wait2p16x w LD A, w ; 7-2 .loop DEC A ; 4 JR NZ, .loop ; 12 endm macro wait4 NOP endm macro wait6 INC DE endm macro wait7 OR $0 endm macro wait8 wait4 wait4 endm macro wait9 LD R, A endm macro wait10 JP .go .go endm macro wait11 wait7 wait4 endm macro wait12 JR .go .go endm macro wait13 wait9 wait4 endm macro wait14 wait7 wait7 endm macro wait15 wait8 wait7 endm macro wait16 wait12 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