import { test, expect } from "bun:test" import type { CircuitJson } from "circuit-json" import { convertCircuitJsonToBpc } from "../lib" // Circuit JSON from the user example const circuitJson = [ { type: "source_group", source_group_id: "source_group_0", is_subcircuit: true, subcircuit_id: "subcircuit_source_group_0", }, { type: "source_port", source_port_id: "source_port_0", name: "VDD", pin_number: 8, port_hints: ["VDD", "pin8", "8"], source_component_id: "source_component_0", subcircuit_id: "subcircuit_source_group_0", subcircuit_connectivity_map_key: "unnamedsubcircuit37_connectivity_net0", }, { type: "source_port", source_port_id: "source_port_1", name: "GND", pin_number: 4, port_hints: ["GND", "pin4", "4"], source_component_id: "source_component_0", subcircuit_id: "subcircuit_source_group_0", subcircuit_connectivity_map_key: "unnamedsubcircuit37_connectivity_net1", }, { type: "source_port", source_port_id: "source_port_2", name: "N_CS", pin_number: 1, port_hints: ["N_CS", "pin1", "1"], source_component_id: "source_component_0", subcircuit_id: "subcircuit_source_group_0", subcircuit_connectivity_map_key: "unnamedsubcircuit37_connectivity_net5", }, { type: "source_port", source_port_id: "source_port_3", name: "CLK", pin_number: 6, port_hints: ["CLK", "pin6", "6"], source_component_id: "source_component_0", subcircuit_id: "subcircuit_source_group_0", subcircuit_connectivity_map_key: "unnamedsubcircuit37_connectivity_net4", }, { type: "source_port", source_port_id: "source_port_4", name: "D0_DI", pin_number: 5, port_hints: ["D0_DI", "pin5", "5"], source_component_id: "source_component_0", subcircuit_id: "subcircuit_source_group_0", subcircuit_connectivity_map_key: "unnamedsubcircuit37_connectivity_net3", }, { type: "source_port", source_port_id: "source_port_5", name: "D1_DO", pin_number: 2, port_hints: ["D1_DO", "pin2", "2"], source_component_id: "source_component_0", subcircuit_id: "subcircuit_source_group_0", subcircuit_connectivity_map_key: "unnamedsubcircuit37_connectivity_net2", }, { type: "source_port", source_port_id: "source_port_6", name: "D2_N_WP", pin_number: 3, port_hints: ["D2_N_WP", "pin3", "3"], source_component_id: "source_component_0", subcircuit_id: "subcircuit_source_group_0", subcircuit_connectivity_map_key: "unnamedsubcircuit37_connectivity_net0", }, { type: "source_port", source_port_id: "source_port_7", name: "D3_N_HOLD", pin_number: 7, port_hints: ["D3_N_HOLD", "pin7", "7"], source_component_id: "source_component_0", subcircuit_id: "subcircuit_source_group_0", subcircuit_connectivity_map_key: "unnamedsubcircuit37_connectivity_net0", }, { type: "source_component", source_component_id: "source_component_0", ftype: "simple_chip", name: "U3", source_group_id: "source_group_0", }, { type: "source_port", source_port_id: "source_port_8", name: "pin1", pin_number: 1, port_hints: ["pin1", "1"], source_component_id: "source_component_1", subcircuit_id: "subcircuit_source_group_0", subcircuit_connectivity_map_key: "unnamedsubcircuit37_connectivity_net1", }, { type: "source_port", source_port_id: "source_port_9", name: "pin2", pin_number: 2, port_hints: ["pin2", "2"], source_component_id: "source_component_1", subcircuit_id: "subcircuit_source_group_0", subcircuit_connectivity_map_key: "unnamedsubcircuit37_connectivity_net0", }, { type: "source_component", source_component_id: "source_component_1", ftype: "simple_capacitor", name: "C20", capacitance: 1e-7, display_capacitance: "100nF", are_pins_interchangeable: true, source_group_id: "source_group_0", }, { type: "source_port", source_port_id: "source_port_10", name: "pin1", pin_number: 1, port_hints: ["anode", "pos", "left", "pin1", "1"], source_component_id: "source_component_2", subcircuit_id: "subcircuit_source_group_0", subcircuit_connectivity_map_key: "unnamedsubcircuit37_connectivity_net5", }, { type: "source_port", source_port_id: "source_port_11", name: "pin2", pin_number: 2, port_hints: ["cathode", "neg", "right", "pin2", "2"], source_component_id: "source_component_2", subcircuit_id: "subcircuit_source_group_0", subcircuit_connectivity_map_key: "unnamedsubcircuit37_connectivity_net0", }, { type: "source_component", source_component_id: "source_component_2", ftype: "simple_resistor", name: "R11", resistance: 100000, display_resistance: "100kΩ", are_pins_interchangeable: true, source_group_id: "source_group_0", }, { type: "source_net", source_net_id: "source_net_0", name: "V3_3", member_source_group_ids: [], subcircuit_id: "subcircuit_source_group_0", subcircuit_connectivity_map_key: "unnamedsubcircuit37_connectivity_net0", }, { type: "source_net", source_net_id: "source_net_1", name: "GND", member_source_group_ids: [], subcircuit_id: "subcircuit_source_group_0", subcircuit_connectivity_map_key: "unnamedsubcircuit37_connectivity_net1", }, { type: "source_net", source_net_id: "source_net_2", name: "FLASH_SDO", member_source_group_ids: [], subcircuit_id: "subcircuit_source_group_0", subcircuit_connectivity_map_key: "unnamedsubcircuit37_connectivity_net2", }, { type: "source_net", source_net_id: "source_net_3", name: "FLASH_SDI", member_source_group_ids: [], subcircuit_id: "subcircuit_source_group_0", subcircuit_connectivity_map_key: "unnamedsubcircuit37_connectivity_net3", }, { type: "source_net", source_net_id: "source_net_4", name: "FLASH_SCK", member_source_group_ids: [], subcircuit_id: "subcircuit_source_group_0", subcircuit_connectivity_map_key: "unnamedsubcircuit37_connectivity_net4", }, { type: "source_net", source_net_id: "source_net_5", name: "FLASH_N_CS", member_source_group_ids: [], subcircuit_id: "subcircuit_source_group_0", subcircuit_connectivity_map_key: "unnamedsubcircuit37_connectivity_net5", }, { type: "source_trace", source_trace_id: "source_trace_0", connected_source_port_ids: ["source_port_0"], connected_source_net_ids: ["source_net_0"], subcircuit_id: "subcircuit_source_group_0", display_name: "chip.U3 > port.VDD to net.V3_3", subcircuit_connectivity_map_key: "unnamedsubcircuit37_connectivity_net0", }, { type: "source_trace", source_trace_id: "source_trace_1", connected_source_port_ids: ["source_port_1"], connected_source_net_ids: ["source_net_1"], subcircuit_id: "subcircuit_source_group_0", display_name: "chip.U3 > port.GND to net.GND", subcircuit_connectivity_map_key: "unnamedsubcircuit37_connectivity_net1", }, { type: "source_trace", source_trace_id: "source_trace_2", connected_source_port_ids: ["source_port_7"], connected_source_net_ids: ["source_net_0"], subcircuit_id: "subcircuit_source_group_0", display_name: "chip.U3 > port.pin7 to net.V3_3", subcircuit_connectivity_map_key: "unnamedsubcircuit37_connectivity_net0", }, { type: "source_trace", source_trace_id: "source_trace_3", connected_source_port_ids: ["source_port_6"], connected_source_net_ids: ["source_net_0"], subcircuit_id: "subcircuit_source_group_0", display_name: "chip.U3 > port.pin3 to net.V3_3", subcircuit_connectivity_map_key: "unnamedsubcircuit37_connectivity_net0", }, { type: "source_trace", source_trace_id: "source_trace_4", connected_source_port_ids: ["source_port_5"], connected_source_net_ids: ["source_net_2"], subcircuit_id: "subcircuit_source_group_0", display_name: "chip.U3 > port.pin2 to net.FLASH_SDO", subcircuit_connectivity_map_key: "unnamedsubcircuit37_connectivity_net2", }, { type: "source_trace", source_trace_id: "source_trace_5", connected_source_port_ids: ["source_port_4"], connected_source_net_ids: ["source_net_3"], subcircuit_id: "subcircuit_source_group_0", display_name: "chip.U3 > port.pin5 to net.FLASH_SDI", subcircuit_connectivity_map_key: "unnamedsubcircuit37_connectivity_net3", }, { type: "source_trace", source_trace_id: "source_trace_6", connected_source_port_ids: ["source_port_3"], connected_source_net_ids: ["source_net_4"], subcircuit_id: "subcircuit_source_group_0", display_name: "chip.U3 > port.pin6 to net.FLASH_SCK", subcircuit_connectivity_map_key: "unnamedsubcircuit37_connectivity_net4", }, { type: "source_trace", source_trace_id: "source_trace_7", connected_source_port_ids: ["source_port_2"], connected_source_net_ids: ["source_net_5"], subcircuit_id: "subcircuit_source_group_0", display_name: "chip.U3 > port.pin1 to net.FLASH_N_CS", subcircuit_connectivity_map_key: "unnamedsubcircuit37_connectivity_net5", }, { type: "source_trace", source_trace_id: "source_trace_8", connected_source_port_ids: ["source_port_9", "source_port_0"], connected_source_net_ids: [], subcircuit_id: "subcircuit_source_group_0", max_length: null, display_name: "capacitor.C20 > port.pin2 to .U3 > .VDD", subcircuit_connectivity_map_key: "unnamedsubcircuit37_connectivity_net0", }, { type: "source_trace", source_trace_id: "source_trace_9", connected_source_port_ids: ["source_port_8", "source_port_1"], connected_source_net_ids: [], subcircuit_id: "subcircuit_source_group_0", max_length: null, display_name: "capacitor.C20 > port.pin1 to .U3 > .GND", subcircuit_connectivity_map_key: "unnamedsubcircuit37_connectivity_net1", }, { type: "source_trace", source_trace_id: "source_trace_10", connected_source_port_ids: ["source_port_11"], connected_source_net_ids: ["source_net_0"], subcircuit_id: "subcircuit_source_group_0", display_name: "resistor.R11 > port.pin2 to net.V3_3", subcircuit_connectivity_map_key: "unnamedsubcircuit37_connectivity_net0", }, { type: "source_trace", source_trace_id: "source_trace_11", connected_source_port_ids: ["source_port_10", "source_port_2"], connected_source_net_ids: [], subcircuit_id: "subcircuit_source_group_0", display_name: "resistor.R11 > port.pin1 to .U3 > .N_CS", subcircuit_connectivity_map_key: "unnamedsubcircuit37_connectivity_net5", }, { type: "schematic_component", schematic_component_id: "schematic_component_0", center: { x: 0, y: 0 }, rotation: 0, size: { width: 2, height: 1.4 }, port_arrangement: { left_side: { pins: [8, 4], direction: "top-to-bottom" }, right_side: { pins: [1, 6, 5, 2, 3, 7], direction: "top-to-bottom" }, }, pin_spacing: 0.2, pin_styles: { pin4: {} }, port_labels: { pin8: "VDD", pin4: "GND", pin1: "N_CS", pin6: "CLK", pin5: "D0_DI", pin2: "D1_DO", pin3: "D2_N_WP", pin7: "D3_N_HOLD", }, source_component_id: "source_component_0", schematic_group_id: "schematic_group_0", }, { type: "schematic_text", schematic_text_id: "schematic_text_0", text: "", schematic_component_id: "schematic_component_0", anchor: "left", rotation: 0, position: { x: -1, y: -0.83 }, color: "#006464", font_size: 0.18, }, { type: "schematic_text", schematic_text_id: "schematic_text_1", text: "U3", schematic_component_id: "schematic_component_0", anchor: "left", rotation: 0, position: { x: -1, y: 0.83 }, color: "#006464", font_size: 0.18, }, { type: "schematic_component", schematic_component_id: "schematic_component_1", center: { x: -3, y: 0 }, size: { width: 0.5291665999999999, height: 1.0583333000000001 }, source_component_id: "source_component_1", symbol_name: "capacitor_up", symbol_display_value: "100nF", schematic_group_id: "schematic_group_0", }, { type: "schematic_component", schematic_component_id: "schematic_component_2", center: { x: 2, y: 1 }, size: { width: 0.40790845000000175, height: 1.0583332999999997 }, source_component_id: "source_component_2", symbol_name: "boxresistor_up", symbol_display_value: "100kΩ", schematic_group_id: "schematic_group_0", }, { type: "schematic_group", schematic_group_id: "schematic_group_0", is_subcircuit: true, subcircuit_id: "subcircuit_source_group_0", name: "UNNAMED_subcircuit_source_group_0", center: { x: 0, y: 0 }, width: 0, height: 0, schematic_component_ids: [], source_group_id: "source_group_0", }, { type: "schematic_port", schematic_port_id: "schematic_port_0", schematic_component_id: "schematic_component_0", center: { x: -1.4, y: 0.42500000000000004 }, source_port_id: "source_port_0", facing_direction: "left", distance_from_component_edge: 0.4, side_of_component: "left", pin_number: 8, true_ccw_index: 0, display_pin_label: "VDD", }, { type: "schematic_port", schematic_port_id: "schematic_port_1", schematic_component_id: "schematic_component_0", center: { x: -1.4, y: -0.42500000000000004 }, source_port_id: "source_port_1", facing_direction: "left", distance_from_component_edge: 0.4, side_of_component: "left", pin_number: 4, true_ccw_index: 1, display_pin_label: "GND", }, { type: "schematic_port", schematic_port_id: "schematic_port_2", schematic_component_id: "schematic_component_0", center: { x: 1.4, y: 0.5 }, source_port_id: "source_port_2", facing_direction: "right", distance_from_component_edge: 0.4, side_of_component: "right", pin_number: 1, true_ccw_index: 7, display_pin_label: "N_CS", }, { type: "schematic_port", schematic_port_id: "schematic_port_3", schematic_component_id: "schematic_component_0", center: { x: 1.4, y: 0.30000000000000004 }, source_port_id: "source_port_3", facing_direction: "right", distance_from_component_edge: 0.4, side_of_component: "right", pin_number: 6, true_ccw_index: 6, display_pin_label: "CLK", }, { type: "schematic_port", schematic_port_id: "schematic_port_4", schematic_component_id: "schematic_component_0", center: { x: 1.4, y: 0.10000000000000009 }, source_port_id: "source_port_4", facing_direction: "right", distance_from_component_edge: 0.4, side_of_component: "right", pin_number: 5, true_ccw_index: 5, display_pin_label: "D0_DI", }, { type: "schematic_port", schematic_port_id: "schematic_port_5", schematic_component_id: "schematic_component_0", center: { x: 1.4, y: -0.09999999999999998 }, source_port_id: "source_port_5", facing_direction: "right", distance_from_component_edge: 0.4, side_of_component: "right", pin_number: 2, true_ccw_index: 4, display_pin_label: "D1_DO", }, { type: "schematic_port", schematic_port_id: "schematic_port_6", schematic_component_id: "schematic_component_0", center: { x: 1.4, y: -0.3 }, source_port_id: "source_port_6", facing_direction: "right", distance_from_component_edge: 0.4, side_of_component: "right", pin_number: 3, true_ccw_index: 3, display_pin_label: "D2_N_WP", }, { type: "schematic_port", schematic_port_id: "schematic_port_7", schematic_component_id: "schematic_component_0", center: { x: 1.4, y: -0.5 }, source_port_id: "source_port_7", facing_direction: "right", distance_from_component_edge: 0.4, side_of_component: "right", pin_number: 7, true_ccw_index: 2, display_pin_label: "D3_N_HOLD", }, { type: "schematic_port", schematic_port_id: "schematic_port_8", schematic_component_id: "schematic_component_1", center: { x: -2.999726650000001, y: -0.5512093000000002 }, source_port_id: "source_port_8", facing_direction: "down", distance_from_component_edge: 0.4, pin_number: 1, }, { type: "schematic_port", schematic_port_id: "schematic_port_9", schematic_component_id: "schematic_component_1", center: { x: -3.0002733499999996, y: 0.5512093000000002 }, source_port_id: "source_port_9", facing_direction: "up", distance_from_component_edge: 0.4, pin_number: 2, }, { type: "schematic_port", schematic_port_id: "schematic_port_10", schematic_component_id: "schematic_component_2", center: { x: 1.9997267500000007, y: 0.44870929999999964 }, source_port_id: "source_port_10", facing_direction: "down", distance_from_component_edge: 0.4, pin_number: 1, display_pin_label: "pos", }, { type: "schematic_port", schematic_port_id: "schematic_port_11", schematic_component_id: "schematic_component_2", center: { x: 2.0002732499999993, y: 1.5512907000000002 }, source_port_id: "source_port_11", facing_direction: "up", distance_from_component_edge: 0.4, pin_number: 2, display_pin_label: "neg", }, ] as unknown as CircuitJson test("infer net labels for provided circuit", () => { const g = convertCircuitJsonToBpc(circuitJson, { inferNetLabels: true }) const netlabelBoxes = g.boxes.filter( (b) => (b as any).boxAttributes?.is_net_label, ) expect(netlabelBoxes.length).toBeGreaterThan(0) })