import * as t from "io-ts"; //#region generated/ChipCNS7263ExtendProperty.d.ts declare const ChipCNS7263ExtendPropertyBase: t.IntersectionC<[t.PartialC<{ IsSetLowEffectGamma: t.Type; }>, t.TypeC<{ REG_LENGTH: t.Type; RegisterArray: t.ArrayC>; }>, t.PartialC<{ OPEN_DET: t.Type; SCAN_LINE: t.Type; PWM_OPT: t.Type; PWM_REV: t.Type; ADJ: t.Type; IGAIN: t.Type; ADJ_Enable: t.Type; KeenPointVoltage: t.Type; FirstLineOffsetCompensation: t.Type; PWM_ALL: t.Type; PWM_ALL_Enable: t.Type; FirstLineOffsetCompensation_Enable: t.Type; OPEN_RST: t.Type; }>]>; /** * Codec for {@link ChipCNS7263ExtendProperty} * @category Codecs * @see Automatically generated from ../decompiled/Nova.LCT.GigabitSystem.ChipCNS7263.decompiled.cs:2129 */ declare const ChipCNS7263ExtendProperty: t.IntersectionC<[t.IntersectionC<[t.PartialC<{ IsSetLowEffectGamma: t.Type; }>, t.TypeC<{ REG_LENGTH: t.Type; RegisterArray: t.ArrayC>; }>, t.PartialC<{ OPEN_DET: t.Type; SCAN_LINE: t.Type; PWM_OPT: t.Type; PWM_REV: t.Type; ADJ: t.Type; IGAIN: t.Type; ADJ_Enable: t.Type; KeenPointVoltage: t.Type; FirstLineOffsetCompensation: t.Type; PWM_ALL: t.Type; PWM_ALL_Enable: t.Type; FirstLineOffsetCompensation_Enable: t.Type; OPEN_RST: t.Type; }>]>, t.PartialC<{ '@_xsi:type': t.LiteralC<"ChipCNS7263ExtendProperty">; }>]>; interface ChipCNS7263ExtendProperty extends t.TypeOf {} //#endregion export { ChipCNS7263ExtendPropertyBase as n, ChipCNS7263ExtendProperty as t }; //# sourceMappingURL=ChipCNS7263ExtendProperty-Cg88q2pj.d.mts.map