/**
 * (c) 2026, Micro:bit Educational Foundation and contributors
 *
 * Derived from dapjs (https://github.com/ARMmbed/dapjs) which is
 * Copyright (c) Arm Limited 2018
 * Copyright (c) Microsoft Corporation
 *
 * SPDX-License-Identifier: MIT
 *
 * See arm-debug.ts for the full dapjs license.
 *
 * Cortex-M processor control via the ARM Debug Interface.
 *
 * CortexM provides high-level operations for controlling an ARM Cortex-M
 * core over SWD: halting, resuming, reading/writing core registers,
 * executing code from RAM, and performing software resets.
 *
 * It communicates entirely through ArmDebug memory-mapped register
 * access — the Cortex-M debug registers (DHCSR, DCRSR, DCRDR, etc.) are
 * memory-mapped in the Private Peripheral Bus region starting at 0xE000_0000.
 */
import { type ArmDebug } from "./arm-debug.js";
export declare const DFSR = 3758157104;
export declare const DHCSR = 3758157296;
export declare const DCRSR = 3758157300;
export declare const DCRDR = 3758157304;
export declare const C_DEBUGEN: number;
export declare const C_HALT: number;
export declare const S_REGRDY: number;
export declare const S_HALT: number;
export declare const DBGKEY: number;
export declare const DFSR_HALTED: number;
export declare const DFSR_BKPT: number;
export declare const DFSR_DWTTRAP: number;
export declare const REGWnR: number;
export declare const DEMCR = 3758157308;
export declare const DEMCR_VC_CORERESET: number;
export declare const NVIC_AIRCR = 3758157068;
export declare const NVIC_AIRCR_VECTKEY: number;
export declare const NVIC_AIRCR_SYSRESETREQ: number;
export declare const S_RESET_ST: number;
export declare const CoreRegister: {
    readonly SP: 13;
    readonly LR: 14;
    readonly PC: 15;
    readonly PSR: 16;
};
export declare class CortexM {
    private adi;
    constructor(adi: ArmDebug);
    private enableDebug;
    isHalted(): Promise<boolean>;
    halt(wait?: boolean, timeout?: number): Promise<void>;
    resume(wait?: boolean, timeout?: number): Promise<void>;
    readCoreRegister(register: number): Promise<number>;
    writeCoreRegister(register: number, value: number): Promise<void>;
    waitForHalt(timeout?: number): Promise<void>;
    /**
     * Upload code to target RAM, set up registers, resume execution,
     * and wait for the core to halt (typically on a BKPT instruction).
     */
    execute(address: number, code: Uint32Array, sp: number, pc: number, lr: number, ...registers: number[]): Promise<void>;
    /**
     * Software reset by writing to NVIC_AIRCR.
     * Waits for the system to come out of reset.
     */
    softwareReset(): Promise<void>;
    /**
     * Reset the target, optionally halting the core on reset.
     */
    reset(halt?: boolean): Promise<void>;
}