{
  "options": {
    "directed": true,
    "multigraph": false,
    "compound": true
  },
  "nodes": [
    {
      "v": "EXAMPLE1",
      "value": {}
    },
    {
      "v": "0_STDIN",
      "value": {
        "id": "io/stdin",
        "version": "0.1.0",
        "inputPorts": {},
        "outputPorts": {
          "stdin/output": "string"
        },
        "atomic": true
      },
      "parent": "EXAMPLE1"
    },
    {
      "v": "1_INC",
      "value": {
        "id": "math/inc",
        "version": "0.1.0",
        "inputPorts": {
          "inc/i": "int"
        },
        "outputPorts": {
          "inc/inc": "int"
        },
        "atomic": false
      },
      "parent": "EXAMPLE1"
    },
    {
      "v": "2_STDOUT",
      "value": {
        "id": "io/stdout",
        "version": "0.1.0",
        "inputPorts": {
          "stdout/input": "string"
        },
        "outputPorts": {},
        "atomic": true
      },
      "parent": "EXAMPLE1"
    },
    {
      "v": "3_ADD",
      "value": {
        "id": "math/add",
        "version": "0.1.0",
        "inputPorts": {
          "add/s1": "int",
          "add/s2": "int"
        },
        "outputPorts": {
          "add/sum": "int"
        },
        "atomic": true
      },
      "parent": "1_INC"
    },
    {
      "v": "4_CONST1",
      "value": {
        "id": "math/const1",
        "version": "0.1.0",
        "inputPorts": {},
        "outputPorts": {
          "const1/output": "int"
        },
        "atomic": true
      },
      "parent": "1_INC"
    },
    {
      "v": "1_INC_PORT_i",
      "value": {
        "nodeType": "inPort",
        "portName": "inc/i"
      },
      "parent": "EXAMPLE1"
    },
    {
      "v": "0_STDIN_PORT_output",
      "value": {
        "nodeType": "outPort",
        "portName": "stdin/output"
      },
      "parent": "EXAMPLE1"
    },
    {
      "v": "2_STDOUT_PORT_input",
      "value": {
        "nodeType": "inPort",
        "portName": "stdout/input"
      },
      "parent": "EXAMPLE1"
    },
    {
      "v": "1_INC_PORT_inc",
      "value": {
        "nodeType": "outPort",
        "portName": "inc/inc"
      },
      "parent": "EXAMPLE1"
    },
    {
      "v": "3_ADD_PORT_s1",
      "value": {
        "nodeType": "inPort",
        "portName": "add/s1"
      },
      "parent": "1_INC"
    },
    {
      "v": "3_ADD_PORT_s2",
      "value": {
        "nodeType": "inPort",
        "portName": "add/s2"
      },
      "parent": "1_INC"
    },
    {
      "v": "4_CONST1_PORT_const1",
      "value": {
        "nodeType": "outPort",
        "portName": "const1/output"
      },
      "parent": "1_INC"
    },
    {
      "v": "3_ADD_PORT_sum",
      "value": {
        "nodeType": "outPort",
        "portName": "add/sum"
      },
      "parent": "1_INC"
    },
    {
      "v": "0_STDIN_PORT_output:1_INC_PORT_i_1",
      "value": {
        "nodeType": "process",
        "id": "translator/string_to_int",
        "atomic": "true"
      },
      "parent": "EXAMPLE1"
    },
    {
      "v": "0_STDIN_PORT_output:1_INC_PORT_i_1_PORT_in",
      "value": {
        "nodeType": "inPort",
        "portName": "input",
        "isTrans": true
      },
      "parent": "EXAMPLE1"
    },
    {
      "v": "0_STDIN_PORT_output:1_INC_PORT_i_1_PORT_out",
      "value": {
        "nodeType": "outPort",
        "portName": "output",
        "isTrans": true
      },
      "parent": "EXAMPLE1"
    },
    {
      "v": "1_INC_PORT_inc:2_STDOUT_PORT_input_1",
      "value": {
        "nodeType": "process",
        "id": "translator/int_to_string",
        "atomic": "true"
      },
      "parent": "EXAMPLE1"
    },
    {
      "v": "1_INC_PORT_inc:2_STDOUT_PORT_input_1_PORT_in",
      "value": {
        "nodeType": "inPort",
        "portName": "input",
        "isTrans": true
      },
      "parent": "EXAMPLE1"
    },
    {
      "v": "1_INC_PORT_inc:2_STDOUT_PORT_input_1_PORT_out",
      "value": {
        "nodeType": "outPort",
        "portName": "output",
        "isTrans": true
      },
      "parent": "EXAMPLE1"
    }
  ],
  "edges": [
    {
      "v": "0_STDIN",
      "w": "0_STDIN_PORT_output"
    },
    {
      "v": "2_STDOUT_PORT_input",
      "w": "2_STDOUT"
    },
    {
      "v": "3_ADD_PORT_s1",
      "w": "3_ADD"
    },
    {
      "v": "1_INC_PORT_i",
      "w": "3_ADD_PORT_s1"
    },
    {
      "v": "3_ADD_PORT_s2",
      "w": "3_ADD"
    },
    {
      "v": "4_CONST1",
      "w": "4_CONST1_PORT_const1"
    },
    {
      "v": "4_CONST1_PORT_const1",
      "w": "3_ADD_PORT_s2"
    },
    {
      "v": "3_ADD",
      "w": "3_ADD_PORT_sum"
    },
    {
      "v": "3_ADD_PORT_sum",
      "w": "1_INC_PORT_inc"
    },
    {
      "v": "0_STDIN_PORT_output:1_INC_PORT_i_1_PORT_in",
      "w": "0_STDIN_PORT_output:1_INC_PORT_i_1"
    },
    {
      "v": "0_STDIN_PORT_output:1_INC_PORT_i_1",
      "w": "0_STDIN_PORT_output:1_INC_PORT_i_1_PORT_out"
    },
    {
      "v": "0_STDIN_PORT_output",
      "w": "0_STDIN_PORT_output:1_INC_PORT_i_1_PORT_in"
    },
    {
      "v": "0_STDIN_PORT_output:1_INC_PORT_i_1_PORT_out",
      "w": "1_INC_PORT_i"
    },
    {
      "v": "1_INC_PORT_inc:2_STDOUT_PORT_input_1_PORT_in",
      "w": "1_INC_PORT_inc:2_STDOUT_PORT_input_1"
    },
    {
      "v": "1_INC_PORT_inc:2_STDOUT_PORT_input_1",
      "w": "1_INC_PORT_inc:2_STDOUT_PORT_input_1_PORT_out"
    },
    {
      "v": "1_INC_PORT_inc",
      "w": "1_INC_PORT_inc:2_STDOUT_PORT_input_1_PORT_in"
    },
    {
      "v": "1_INC_PORT_inc:2_STDOUT_PORT_input_1_PORT_out",
      "w": "2_STDOUT_PORT_input"
    }
  ]
}